arm64: dts: qcom: sc7280: Add Display Port node

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1640361793-26486-5-git-send-email-quic_sbillaka@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ba4dc230e037611be7645bf6bd78c858e681657c..5b9312ddf5cfd565e9ee03276f7bfe0c5809db5a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2768,8 +2768,8 @@
                                 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
                                 <&mdss_dsi_phy 0>,
                                 <&mdss_dsi_phy 1>,
-                                <0>,
-                                <0>,
+                                <&dp_phy 0>,
+                                <&dp_phy 1>,
                                 <&mdss_edp_phy 0>,
                                 <&mdss_edp_phy 1>;
                        clock-names = "bi_tcxo",
@@ -2866,6 +2866,13 @@
                                                        remote-endpoint = <&edp_in>;
                                                };
                                        };
+
+                                       port@2 {
+                                               reg = <2>;
+                                               dpu_intf0_out: endpoint {
+                                                       remote-endpoint = <&dp_in>;
+                                               };
+                                       };
                                };
 
                                mdp_opp_table: opp-table {
@@ -3077,6 +3084,79 @@
 
                                status = "disabled";
                        };
+
+                       mdss_dp: displayport-controller@ae90000 {
+                               compatible = "qcom,sc7280-dp";
+
+                               reg = <0 0x0ae90000 0 0x1400>;
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <12>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+                                        <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+                               clock-names =   "core_iface",
+                                               "core_aux",
+                                               "ctrl_link",
+                                               "ctrl_link_iface",
+                                               "stream_pixel";
+                               #clock-cells = <1>;
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+                               assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+                               phys = <&dp_phy>;
+                               phy-names = "dp";
+
+                               operating-points-v2 = <&dp_opp_table>;
+                               power-domains = <&rpmhpd SC7280_CX>;
+
+                               #sound-dai-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       port@0 {
+                                               reg = <0>;
+                                               dp_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf0_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               dp_out: endpoint { };
+                                       };
+                               };
+
+                               dp_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-160000000 {
+                                               opp-hz = /bits/ 64 <160000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+
+                                       opp-270000000 {
+                                               opp-hz = /bits/ 64 <270000000>;
+                                               required-opps = <&rpmhpd_opp_svs>;
+                                       };
+
+                                       opp-540000000 {
+                                               opp-hz = /bits/ 64 <540000000>;
+                                               required-opps = <&rpmhpd_opp_svs_l1>;
+                                       };
+
+                                       opp-810000000 {
+                                               opp-hz = /bits/ 64 <810000000>;
+                                               required-opps = <&rpmhpd_opp_nom>;
+                                       };
+                               };
+                       };
                };
 
                pdc: interrupt-controller@b220000 {
@@ -3179,6 +3259,12 @@
                                bias-pull-up;
                        };
 
+                       dp_hot_plug_det: dp-hot-plug-det {
+                               pins = "gpio47";
+                               function = "dp_hot";
+                               bias-disable;
+                       };
+
                        qspi_clk: qspi-clk {
                                pins = "gpio14";
                                function = "qspi_clk";