* the communication processor devices.
  */
 cpm2_map_t *cpm2_immr;
+intctl_cpm2_t *cpm2_intctl;
 
 #define CPM_MAP_SIZE   (0x40000)       /* 256k - the PQ3 reserve this amount
                                           of space for CPM as it is larger
 cpm2_reset(void)
 {
        cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
+       cpm2_intctl = cpm2_map(im_intctl);
 
        /* Reclaim the DP memory for our use.
         */
        /* This is good enough to get SMCs running.....
        */
        if (brg < 4) {
-               bp = (uint *)&cpm2_immr->im_brgc1;
+               bp = cpm2_map_size(im_brgc1, 16);
        } else {
-               bp = (uint *)&cpm2_immr->im_brgc5;
+               bp = cpm2_map_size(im_brgc5, 16);
                brg -= 4;
        }
        bp += brg;
        *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
+
+       cpm2_unmap(bp);
 }
 
 /* This function is used to set high speed synchronous baud rate
        volatile uint   *bp;
 
        if (brg < 4) {
-               bp = (uint *)&cpm2_immr->im_brgc1;
+               bp = cpm2_map_size(im_brgc1, 16);
        }
        else {
-               bp = (uint *)&cpm2_immr->im_brgc5;
+               bp = cpm2_map_size(im_brgc5, 16);
                brg -= 4;
        }
        bp += brg;
        *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
        if (div16)
                *bp |= CPM_BRG_DIV16;
+
+       cpm2_unmap(bp);
 }
 
 /*
  * until the memory subsystem goes up... */
 static rh_block_t cpm_boot_dpmem_rh_block[16];
 static rh_info_t cpm_dpmem_info;
+static u8* im_dprambase;
 
 static void cpm2_dpinit(void)
 {
        spin_lock_init(&cpm_dpmem_lock);
 
+       im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
+
        /* initialize the info header */
        rh_init(&cpm_dpmem_info, 1,
                        sizeof(cpm_boot_dpmem_rh_block) /
 
 void *cpm_dpram_addr(uint offset)
 {
-       return (void *)&cpm2_immr->im_dprambase[offset];
+       return (void *)(im_dprambase + offset);
 }
 EXPORT_SYMBOL(cpm_dpram_addr);
 
        bit = irq_to_siubit[irq_nr];
        word = irq_to_siureg[irq_nr];
 
-       simr = &(cpm2_immr->im_intctl.ic_simrh);
+       simr = &(cpm2_intctl->ic_simrh);
        ppc_cached_irq_mask[word] &= ~(1 << bit);
        simr[word] = ppc_cached_irq_mask[word];
 }
        bit = irq_to_siubit[irq_nr];
        word = irq_to_siureg[irq_nr];
 
-       simr = &(cpm2_immr->im_intctl.ic_simrh);
+       simr = &(cpm2_intctl->ic_simrh);
        ppc_cached_irq_mask[word] |= 1 << bit;
        simr[word] = ppc_cached_irq_mask[word];
 }
        bit = irq_to_siubit[irq_nr];
        word = irq_to_siureg[irq_nr];
 
-       simr = &(cpm2_immr->im_intctl.ic_simrh);
-       sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
+       simr = &(cpm2_intctl->ic_simrh);
+       sipnr = &(cpm2_intctl->ic_sipnrh);
        ppc_cached_irq_mask[word] &= ~(1 << bit);
        simr[word] = ppc_cached_irq_mask[word];
        sipnr[word] = 1 << bit;
                bit = irq_to_siubit[irq_nr];
                word = irq_to_siureg[irq_nr];
 
-               simr = &(cpm2_immr->im_intctl.ic_simrh);
+               simr = &(cpm2_intctl->ic_simrh);
                ppc_cached_irq_mask[word] |= 1 << bit;
                simr[word] = ppc_cached_irq_mask[word];
                /*
        int irq;
        unsigned long bits;
 
-       /* For CPM2, read the SIVEC register and shift the bits down
-        * to get the irq number.*/
-       bits = cpm2_immr->im_intctl.ic_sivec;
-       irq = bits >> 26;
+       /* For CPM2, read the SIVEC register and shift the bits down
+         * to get the irq number.         */
+        bits = cpm2_intctl->ic_sivec;
+        irq = bits >> 26;
 
        if (irq == 0)
                return(-1);
 
        /* Mask out everything */
 
-       cpm2_immr->im_intctl.ic_simrh = 0x00000000;
-       cpm2_immr->im_intctl.ic_simrl = 0x00000000;
+       cpm2_intctl->ic_simrh = 0x00000000;
+       cpm2_intctl->ic_simrl = 0x00000000;
 
        wmb();
 
        /* Ack everything */
-       cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff;
-       cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff;
+       cpm2_intctl->ic_sipnrh = 0xffffffff;
+       cpm2_intctl->ic_sipnrl = 0xffffffff;
        wmb();
 
        /* Dummy read of the vector */
-       i = cpm2_immr->im_intctl.ic_sivec;
+       i = cpm2_intctl->ic_sivec;
        rmb();
 
        /* Initialize the default interrupt mapping priorities,
         * in case the boot rom changed something on us.
         */
-       cpm2_immr->im_intctl.ic_sicr = 0;
-       cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
-       cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
+       cpm2_intctl->ic_sicr = 0;
+       cpm2_intctl->ic_scprrh = 0x05309770;
+       cpm2_intctl->ic_scprrl = 0x05309770;
 
        /* create a legacy host */
        if (node)
 
 
 void cpm_line_cr_cmd(int line, int cmd)
 {
-       volatile cpm_cpm2_t *cp = cpmp;
        ulong val;
+       volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
+
 
        switch (line) {
        case UART_SMC1:
        }
        cp->cp_cpcr = val;
        while (cp->cp_cpcr & CPM_CR_FLG) ;
+
+       cpm2_unmap(cp);
 }
 
 void smc1_lineif(struct uart_cpm_port *pinfo)
 {
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
 
        /* SMC1 is only on port D */
        io->iop_ppard |= 0x00c00000;
        io->iop_psord &= ~0x00c00000;
 
        /* Wire BRG1 to SMC1 */
-       cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
+       cpmux->cmx_smr &= 0x0f;
        pinfo->brg = 1;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 void smc2_lineif(struct uart_cpm_port *pinfo)
 {
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
 
        /* SMC2 is only on port A */
        io->iop_ppara |= 0x00c00000;
        io->iop_psora &= ~0x00c00000;
 
        /* Wire BRG2 to SMC2 */
-       cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
+       cpmux->cmx_smr &= 0xf0;
        pinfo->brg = 2;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 void scc1_lineif(struct uart_cpm_port *pinfo)
 {
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
 
        /* Use Port D for SCC1 instead of other functions.  */
        io->iop_ppard |= 0x00000003;
        io->iop_pdird |= 0x00000002;    /* Tx */
 
        /* Wire BRG1 to SCC1 */
-       cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
-       cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
+       cpmux->cmx_scr &= 0x00ffffff;
+       cpmux->cmx_scr |= 0x00000000;
        pinfo->brg = 1;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 void scc2_lineif(struct uart_cpm_port *pinfo)
         * be supported in a sane fashion.
         */
 #ifndef CONFIG_STX_GP3
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
+
        io->iop_pparb |= 0x008b0000;
        io->iop_pdirb |= 0x00880000;
        io->iop_psorb |= 0x00880000;
        io->iop_pdirb &= ~0x00030000;
        io->iop_psorb &= ~0x00030000;
 #endif
-       cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
-       cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
+       cpmux->cmx_scr &= 0xff00ffff;
+       cpmux->cmx_scr |= 0x00090000;
        pinfo->brg = 2;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 void scc3_lineif(struct uart_cpm_port *pinfo)
 {
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
+
        io->iop_pparb |= 0x008b0000;
        io->iop_pdirb |= 0x00880000;
        io->iop_psorb |= 0x00880000;
        io->iop_pdirb &= ~0x00030000;
        io->iop_psorb &= ~0x00030000;
-       cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
-       cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
+       cpmux->cmx_scr &= 0xffff00ff;
+       cpmux->cmx_scr |= 0x00001200;
        pinfo->brg = 3;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 void scc4_lineif(struct uart_cpm_port *pinfo)
 {
-       volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
+       volatile iop_cpm2_t *io = cpm2_map(im_ioport);
+       volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
 
        io->iop_ppard |= 0x00000600;
        io->iop_psord &= ~0x00000600;   /* Tx/Rx */
        io->iop_pdird &= ~0x00000200;   /* Rx */
        io->iop_pdird |= 0x00000400;    /* Tx */
 
-       cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
-       cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
+       cpmux->cmx_scr &= 0xffffff00;
+       cpmux->cmx_scr |= 0x0000001b;
        pinfo->brg = 4;
+
+       cpm2_unmap(cpmux);
+       cpm2_unmap(io);
 }
 
 /*
 /* Setup any dynamic params in the uart desc */
 int cpm_uart_init_portdesc(void)
 {
+#if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
+       u32 addr;
+#endif
        pr_debug("CPM uart[-]:init portdesc\n");
 
        cpm_uart_nr = 0;
 #ifdef CONFIG_SERIAL_CPM_SMC1
-       cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
-       cpm_uart_ports[UART_SMC1].smcup =
-           (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
-       *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
+       cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
        cpm_uart_ports[UART_SMC1].port.mapbase =
-           (unsigned long)&cpm2_immr->im_smc[0];
+           (unsigned long)cpm_uart_ports[UART_SMC1].smcp;
+
+       cpm_uart_ports[UART_SMC1].smcup =
+           (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
+       addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
+       *addr = PROFF_SMC1;
+       cpm2_unmap(addr);
+
        cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
        cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
        cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
 #endif
 
 #ifdef CONFIG_SERIAL_CPM_SMC2
-       cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
-       cpm_uart_ports[UART_SMC2].smcup =
-           (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
-       *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
+       cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
        cpm_uart_ports[UART_SMC2].port.mapbase =
-           (unsigned long)&cpm2_immr->im_smc[1];
+           (unsigned long)cpm_uart_ports[UART_SMC2].smcp;
+
+       cpm_uart_ports[UART_SMC2].smcup =
+           (smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
+       addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
+       *addr = PROFF_SMC2;
+       cpm2_unmap(addr);
+
        cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
        cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
        cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
 #endif
 
 #ifdef CONFIG_SERIAL_CPM_SCC1
-       cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
-       cpm_uart_ports[UART_SCC1].sccup =
-           (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
+       cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
        cpm_uart_ports[UART_SCC1].port.mapbase =
-           (unsigned long)&cpm2_immr->im_scc[0];
+           (unsigned long)cpm_uart_ports[UART_SCC1].sccp;
+       cpm_uart_ports[UART_SCC1].sccup =
+           (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
+
        cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
            ~(UART_SCCM_TX | UART_SCCM_RX);
        cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
 #endif
 
 #ifdef CONFIG_SERIAL_CPM_SCC2
-       cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
-       cpm_uart_ports[UART_SCC2].sccup =
-           (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
+       cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
        cpm_uart_ports[UART_SCC2].port.mapbase =
-           (unsigned long)&cpm2_immr->im_scc[1];
+           (unsigned long)cpm_uart_ports[UART_SCC2].sccp;
+       cpm_uart_ports[UART_SCC2].sccup =
+           (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
+
        cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
            ~(UART_SCCM_TX | UART_SCCM_RX);
        cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
 #endif
 
 #ifdef CONFIG_SERIAL_CPM_SCC3
-       cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
-       cpm_uart_ports[UART_SCC3].sccup =
-           (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
+       cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
        cpm_uart_ports[UART_SCC3].port.mapbase =
-           (unsigned long)&cpm2_immr->im_scc[2];
+           (unsigned long)cpm_uart_ports[UART_SCC3].sccp;
+       cpm_uart_ports[UART_SCC3].sccup =
+           (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
+
        cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
            ~(UART_SCCM_TX | UART_SCCM_RX);
        cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
 #endif
 
 #ifdef CONFIG_SERIAL_CPM_SCC4
-       cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
-       cpm_uart_ports[UART_SCC4].sccup =
-           (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
+       cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
        cpm_uart_ports[UART_SCC4].port.mapbase =
-           (unsigned long)&cpm2_immr->im_scc[3];
+           (unsigned long)cpm_uart_ports[UART_SCC4].sccp;
+       cpm_uart_ports[UART_SCC4].sccup =
+           (scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
+
        cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
            ~(UART_SCCM_TX | UART_SCCM_RX);
        cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=