powerpc/8xx: Allow large TLBs with DEBUG_PAGEALLOC

DEBUG_PAGEALLOC only manages RW data.

Text and RO data can still be mapped with hugepages and pinned TLB.

In order to map with hugepages, also enforce a 512kB data alignment
minimum. That's a trade-off between size of speed, taking into
account that DEBUG_PAGEALLOC is a debug option. Anyway the alignment
is still tunable.

We also allow tuning of alignment for book3s to limit the complexity
of the test in Kconfig that will anyway disappear in the following
patches once DEBUG_PAGEALLOC is handled together with BATs.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c13256f2d356a316715da61fe089b3623ef217a5.1589866984.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index f5e82629e2cd94ec498ddb09c6e97916f4b4ab78..fcb0a9ae98726518b578a5dabaf751cf0e404ea5 100644 (file)
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -781,8 +781,9 @@ config THREAD_SHIFT
 config DATA_SHIFT_BOOL
        bool "Set custom data alignment"
        depends on ADVANCED_OPTIONS
-       depends on STRICT_KERNEL_RWX
-       depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && !PIN_TLB_TEXT)
+       depends on STRICT_KERNEL_RWX || DEBUG_PAGEALLOC
+       depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && \
+                                    (!PIN_TLB_TEXT || !STRICT_KERNEL_RWX))
        help
          This option allows you to set the kernel data alignment. When
          RAM is mapped by blocks, the alignment needs to fit the size and
@@ -793,10 +794,12 @@ config DATA_SHIFT_BOOL
 config DATA_SHIFT
        int "Data shift" if DATA_SHIFT_BOOL
        default 24 if STRICT_KERNEL_RWX && PPC64
-       range 17 28 if STRICT_KERNEL_RWX && PPC_BOOK3S_32
-       range 19 23 if STRICT_KERNEL_RWX && PPC_8xx
+       range 17 28 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC) && PPC_BOOK3S_32
+       range 19 23 if (STRICT_KERNEL_RWX || DEBUG_PAGEALLOC) && PPC_8xx
        default 22 if STRICT_KERNEL_RWX && PPC_BOOK3S_32
        default 23 if STRICT_KERNEL_RWX && PPC_8xx
+       default 23 if DEBUG_PAGEALLOC && PPC_8xx && PIN_TLB_DATA
+       default 19 if DEBUG_PAGEALLOC && PPC_8xx
        default PPC_PAGE_SHIFT
        help
          On Book3S 32 (603+), DBATs are used to map kernel text and rodata RO.

diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index a6991ef8727d632c988427f18caaf72860bb6681..8977a7c2543dd7ebe155ce3f66e670533fe6d950 100644 (file)
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -96,11 +96,14 @@ static void __init MMU_setup(void)
        if (strstr(boot_command_line, "noltlbs")) {
                __map_without_ltlbs = 1;
        }
+       if (IS_ENABLED(CONFIG_PPC_8xx))
+               return;
+
        if (debug_pagealloc_enabled()) {
                __map_without_bats = 1;
                __map_without_ltlbs = 1;
        }
-       if (strict_kernel_rwx_enabled() && !IS_ENABLED(CONFIG_PPC_8xx))
+       if (strict_kernel_rwx_enabled())
                __map_without_ltlbs = 1;
 }
 

diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index d8697f535c3e958154e3da3b578eb0adc57822c9..286441bbbe49f90a83323c7fa0c363209dac98ee 100644 (file)
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -150,7 +150,8 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
 {
        unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M);
        unsigned long sinittext = __pa(_sinittext);
-       unsigned long boundary = strict_kernel_rwx_enabled() ? sinittext : etext8;
+       bool strict_boundary = strict_kernel_rwx_enabled() || debug_pagealloc_enabled();
+       unsigned long boundary = strict_boundary ? sinittext : etext8;
        unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M);
 
        WARN_ON(top < einittext8);
@@ -161,8 +162,12 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
                return 0;
 
        mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, true);
-       mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL_TEXT, true);
-       mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true);
+       if (debug_pagealloc_enabled()) {
+               top = boundary;
+       } else {
+               mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL_TEXT, true);
+               mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true);
+       }
 
        if (top > SZ_32M)
                memblock_set_current_limit(top);

diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 05669f2fadce924ec2702928114f4a9d0fee18a4..abb2b45b2789ebbc67f786f5b40e2cdc41f1659a 100644 (file)
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -167,7 +167,7 @@ menu "8xx advanced setup"
 
 config PIN_TLB
        bool "Pinned Kernel TLBs"
-       depends on ADVANCED_OPTIONS && !DEBUG_PAGEALLOC
+       depends on ADVANCED_OPTIONS
        help
          On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
          table 4 TLBs can be pinned.