* @hop_masks: array holds HOPs masks.
* @last_mask: mask to get the bit indicating this is the last hop.
* @pgt_size: size for page tables.
+ * @supported_pages_mask: bitmask for supported page size (relevant only for MMUs
+ * supporting multiple page size).
* @page_size: default page size used to allocate memory.
* @num_hops: The amount of hops supported by the translation table.
* @hop_table_size: HOP table size.
u64 hop_masks[MMU_HOP_MAX];
u64 last_mask;
u64 pgt_size;
+ u64 supported_pages_mask;
u32 page_size;
u32 num_hops;
u32 hop_table_size;
* @get_sob_addr: get SOB base address offset.
* @set_pci_memory_regions: setting properties of PCI memory regions
* @get_stream_master_qid_arr: get pointer to stream masters QID array
- * @get_valid_dram_page_orders: get valid device memory allocation page orders
* @access_dev_mem: access device memory
* @set_dram_bar_base: set the base of the DRAM BAR
*/
u32* (*get_stream_master_qid_arr)(void);
int (*mmu_get_real_page_size)(struct hl_device *hdev, struct hl_mmu_properties *mmu_prop,
u32 page_size, u32 *real_page_size, bool is_dram_addr);
- void (*get_valid_dram_page_orders)(struct hl_info_dev_memalloc_page_sizes *info);
int (*access_dev_mem)(struct hl_device *hdev, struct pci_mem_region *region,
enum pci_region region_type, u64 addr, u64 *val, enum debugfs_access_type acc_type);
u64 (*set_dram_bar_base)(struct hl_device *hdev, u64 addr);
* For this reason for all ASICs that not support multiple page size the function will
* return an empty bitmask indicating that multiple page sizes is not supported.
*/
- hdev->asic_funcs->get_valid_dram_page_orders(&info);
+ info.page_order_bitmask = hdev->asic_prop.dmmu.supported_pages_mask;
return copy_to_user(out, &info, min_t(size_t, max_size, sizeof(info))) ? -EFAULT : 0;
}
static int set_alloc_page_size(struct hl_device *hdev, struct hl_mem_in *args, u32 *page_size)
{
struct asic_fixed_properties *prop = &hdev->asic_prop;
- u32 psize;
+ u64 psize;
/*
* for ASIC that supports setting the allocation page size by user we will address
psize = args->alloc.page_size;
if (!is_power_of_2(psize)) {
- dev_err(hdev->dev, "user page size (%#x) is not power of 2\n", psize);
+ dev_err(hdev->dev, "user page size (%#llx) is not power of 2\n", psize);
return -EINVAL;
}
} else {
return gaudi_stream_master;
}
-static void gaudi_get_valid_dram_page_orders(struct hl_info_dev_memalloc_page_sizes *info)
-{
- /* set 0 since multiple pages are not supported */
- info->page_order_bitmask = 0;
-}
-
static ssize_t infineon_ver_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct hl_device *hdev = dev_get_drvdata(dev);
.set_pci_memory_regions = gaudi_set_pci_memory_regions,
.get_stream_master_qid_arr = gaudi_get_stream_master_qid_arr,
.mmu_get_real_page_size = hl_mmu_get_real_page_size,
- .get_valid_dram_page_orders = gaudi_get_valid_dram_page_orders,
.access_dev_mem = hl_access_dev_mem,
.set_dram_bar_base = gaudi_set_hbm_bar_base,
};
return NULL;
}
-static void goya_get_valid_dram_page_orders(struct hl_info_dev_memalloc_page_sizes *info)
-{
- /* set 0 since multiple pages are not supported */
- info->page_order_bitmask = 0;
-}
-
static int goya_get_monitor_dump(struct hl_device *hdev, void *data)
{
return -EOPNOTSUPP;
.set_pci_memory_regions = goya_set_pci_memory_regions,
.get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
.mmu_get_real_page_size = hl_mmu_get_real_page_size,
- .get_valid_dram_page_orders = goya_get_valid_dram_page_orders,
.access_dev_mem = hl_access_dev_mem,
.set_dram_bar_base = goya_set_ddr_bar_base,
};