drm/i915/psr: Include some basic PSR information in the state dump
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 24 Nov 2023 08:27:31 +0000 (10:27 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 29 Nov 2023 15:02:23 +0000 (17:02 +0200)
Currently no one can figure out what the PSR code is doing since
we're including any of it in the basic state dump. Add at least the
bare minimum there.

v2: Also dump has_panel_replay (Jouni)

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231124082735.25470-1-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

index 30336453041d1beddacca4acef101f5f0da6a660..30b8ddeae8cef0d8cde9ec95016c525ef3b6aaad 100644 (file)
@@ -264,6 +264,12 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 
                drm_dbg_kms(&i915->drm, "sdp split: %s\n",
                            str_enabled_disabled(pipe_config->sdp_split_enable));
+
+               drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",
+                           str_enabled_disabled(pipe_config->has_psr),
+                           str_enabled_disabled(pipe_config->has_psr2),
+                           str_enabled_disabled(pipe_config->has_panel_replay),
+                           str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
        }
 
        drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",