clk: qcom: clk-hfpll: use poll_timeout macro

Use regmap_read_poll_timeout macro instead of do-while structure to tidy
things up. Also set a timeout to prevent any sort of system stall.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com

diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
index e847d586a73aef9ee29b1c50a12a42f0e818b987..7dd17c184b690749610579f1d672c99aa939ca7b 100644 (file)
--- a/drivers/clk/qcom/clk-hfpll.c
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct clk_hw *hw)
        regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
 
        /* Wait for PLL to lock. */
-       if (hd->status_reg) {
-               do {
-                       regmap_read(regmap, hd->status_reg, &val);
-               } while (!(val & BIT(hd->lock_bit)));
-       } else {
+       if (hd->status_reg)
+               /*
+                * Busy wait. Should never timeout, we add a timeout to
+                * prevent any sort of stall.
+                */
+               regmap_read_poll_timeout(regmap, hd->status_reg, val,
+                                        !(val & BIT(hd->lock_bit)), 0,
+                                        100 * USEC_PER_MSEC);
+       else
                udelay(60);
-       }
 
        /* Enable PLL output. */
        regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);