drm/amd/display: Enable CM low mem power optimization

[WHY & HOW]
MPC MCM low mem power optimization still causes color distortion on
first SCE enablement, only forces light sleep for it.

DPP low memory power optimization still needs this bit to save power.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Yihan Zhu <yihan.zhu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 994b21ed272f175318a0b3295ac1c1e052a6b95d..1a2adb3547182bdff5a55c2391d91f225673103e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -71,21 +71,24 @@ void mpc32_power_on_blnd_lut(
 {
        struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 
+/*
        if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
                if (power_on) {
                        REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
                        REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
                } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
-                       ASSERT(false);
-                       /* TODO: change to mpc
-                        *  dpp_base->ctx->dc->optimized_required = true;
-                        *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
-                        */
+                       //TODO: change to mpc
+                       dpp_base->ctx->dc->optimized_required = true;
+                       dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
                }
        } else {
                REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
                                MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
        }
+*/
+
+       REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
+                       MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
 }
 
 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
index c7e011d26d41780262c06ce59dee7f13b3de8997..7a3faf2b1f068f5bc92363fbd9be3f60e87e06c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
@@ -724,7 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .i2c = true,
                        .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
                        .dscl = true,
-                       .cm = false,
+                       .cm = true,
                        .mpc = true,
                        .optc = true,
                        .vpg = true,