drm: rcar-du: Stop accessing non-existent registers on gen4

The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index b7dd59fe119e630b85e764972d61ed66f5ba5bc0..008e172ed43b35adca65a356fbb06d6fc402febe 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -298,10 +298,12 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
                escr = params.escr;
        }
 
-       dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
+       if (rcdu->info->gen < 4) {
+               dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 
-       rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
-       rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
+               rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
+               rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
+       }
 
        /* Signal polarities */
        dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 6da01760ede51bdf2d17fbfb3f1c98cd90285001..152602236377b6fc481cc81546606efeb73d3024 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -148,19 +148,23 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
        }
        rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
 
-       rcar_du_group_setup_pins(rgrp);
+       if (rcdu->info->gen < 4)
+               rcar_du_group_setup_pins(rgrp);
 
-       /*
-        * TODO: Handle routing of the DU output to CMM dynamically, as we
-        * should bypass CMM completely when no color management feature is
-        * used.
-        */
-       defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
-                (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
-       rcar_du_group_write(rgrp, DEFR7, defr7);
+       if (rcdu->info->gen < 4) {
+               /*
+                * TODO: Handle routing of the DU output to CMM dynamically, as
+                * we should bypass CMM completely when no color management
+                * feature is used.
+                */
+               defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
+                        (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
+               rcar_du_group_write(rgrp, DEFR7, defr7);
+       }
 
        if (rcdu->info->gen >= 2) {
-               rcar_du_group_setup_defr8(rgrp);
+               if (rcdu->info->gen < 4)
+                       rcar_du_group_setup_defr8(rgrp);
                rcar_du_group_setup_didsr(rgrp);
        }