x86/perf/zhaoxin: Add stepping check for ZXC

Some of Nano series processors will lead GP when accessing
PMC fixed counter. Meanwhile, their hardware support for PMC
has not announced externally. So exclude Nano CPUs from ZXC
by checking stepping information. This is an unambiguous way
to differentiate between ZXC and Nano CPUs.

Following are Nano and ZXC FMS information:
Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
ZXC FMS:  Family=6, Model=F, Stepping=E-F OR
          Family=6, Model=0x19, Stepping=0-3

Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.")
Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com>
Reported-by: Kevin Brace <kevinbrace@gmx.com>
Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389

diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 949d845c922b48282d0414462b47159fca57206d..3e9acdaeed1ec8ed3b68d0d35ccc7300fb001dd2 100644 (file)
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -541,7 +541,13 @@ __init int zhaoxin_pmu_init(void)
 
        switch (boot_cpu_data.x86) {
        case 0x06:
-               if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) {
+               /*
+                * Support Zhaoxin CPU from ZXC series, exclude Nano series through FMS.
+                * Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
+                * ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3
+                */
+               if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) ||
+                       boot_cpu_data.x86_model == 0x19) {
 
                        x86_pmu.max_period = x86_pmu.cntval_mask >> 1;