*csz = L1_CACHE_BYTES >> 2;
 }
 
-bool ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
+static bool
+ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 {
        struct ath5k_softc *sc = common->priv;
        struct platform_device *pdev = to_platform_device(sc->dev);
 
        eeprom += off;
        if (eeprom > eeprom_end)
-               return -EINVAL;
+               return false;
 
        *data = *eeprom;
-       return 0;
+       return true;
 }
 
 int ath5k_hw_read_srev(struct ath5k_hw *ah)
 
 ath5k_eeprom_init_header(struct ath5k_hw *ah)
 {
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-       int ret;
        u16 val;
        u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
 
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
        u32 o = *offset;
        u16 val;
-       int ret, i = 0;
+       int i = 0;
 
        AR5K_EEPROM_READ(o++, val);
        ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
        u32 o = *offset;
        u16 val;
-       int ret;
 
        ee->ee_n_piers[mode] = 0;
        AR5K_EEPROM_READ(o++, val);
        int o = *offset;
        int i = 0;
        u8 freq1, freq2;
-       int ret;
        u16 val;
 
        ee->ee_n_piers[mode] = 0;
 {
        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
        struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
-       int i, ret;
+       int i;
        u16 val;
        u8 mask;
 
        u32 offset;
        u8 i, c;
        u16 val;
-       int ret;
        u8 pd_gains = 0;
 
        /* Count how many curves we have and
        struct ath5k_chan_pcal_info *chinfo;
        u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
        u32 offset;
-       int idx, i, ret;
+       int idx, i;
        u16 val;
        u8 pd_gains = 0;
 
        u8 *rate_target_pwr_num;
        u32 offset;
        u16 val;
-       int ret, i;
+       int i;
 
        offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
        rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
        struct ath5k_edge_power *rep;
        unsigned int fmask, pmask;
        unsigned int ctl_mode;
-       int ret, i, j;
+       int i, j;
        u32 offset;
        u16 val;
 
        u8 mac_d[ETH_ALEN] = {};
        u32 total, offset;
        u16 data;
-       int octet, ret;
+       int octet;
 
-       ret = ath5k_hw_nvram_read(ah, 0x20, &data);
-       if (ret)
-               return ret;
+       AR5K_EEPROM_READ(0x20, data);
 
        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
-               ret = ath5k_hw_nvram_read(ah, offset, &data);
-               if (ret)
-                       return ret;
+               AR5K_EEPROM_READ(offset, data);
 
                total += data;
                mac_d[octet + 1] = data & 0xff;
 
 #define        AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 
 #define AR5K_EEPROM_READ(_o, _v) do {                  \
-       ret = ath5k_hw_nvram_read(ah, (_o), &(_v));     \
-       if (ret)                                        \
-               return ret;                             \
+       if (!ath5k_hw_nvram_read(ah, (_o), &(_v)))      \
+               return -EIO;                            \
 } while (0)
 
 #define AR5K_EEPROM_READ_HDR(_o, _v)                                   \
 
 /*
  * Read from eeprom
  */
-bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
+static bool
+ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
 {
        struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
        u32 status, timeout;
                status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
                if (status & AR5K_EEPROM_STAT_RDDONE) {
                        if (status & AR5K_EEPROM_STAT_RDERR)
-                               return -EIO;
+                               return false;
                        *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
                                        0xffff);
-                       return 0;
+                       return true;
                }
                udelay(15);
        }
 
-       return -ETIMEDOUT;
+       return false;
 }
 
 int ath5k_hw_read_srev(struct ath5k_hw *ah)