drm/amd/display: Setup for mmhubbub3_warmup_mcif with big buffer
authorAlex Hung <alex.hung@amd.com>
Fri, 1 Dec 2023 13:25:37 +0000 (06:25 -0700)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Dec 2023 20:22:35 +0000 (15:22 -0500)
[WHY]
Hardware may require different warmup approaches - big buffer or
individual buffers.

[HOW]
Setup warmup for big buffer when it is required by specific hardware.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

index b45b248808f7bb437709b7bb61de34891e662796..7e5e4be99b6000ea042862c53a1a26306cebdfea 100644 (file)
@@ -8844,6 +8844,7 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm,
                              struct drm_connector_state *new_con_state)
 {
        struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector);
+       struct amdgpu_device *adev = dm->adev;
        struct amdgpu_crtc *acrtc;
        struct dc_writeback_info *wb_info;
        struct pipe_ctx *pipe = NULL;
@@ -8919,6 +8920,11 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm,
        }
 
        wb_info->mcif_buf_params.p_vmid = 1;
+       if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0)) {
+               wb_info->mcif_warmup_params.start_address.quad_part = afb->address;
+               wb_info->mcif_warmup_params.region_size =
+                       wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height;
+       }
        wb_info->mcif_warmup_params.p_vmid = 1;
        wb_info->writeback_source_plane = pipe->plane_state;