drm/i915/display: Compare the readout dsc pps params

With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.

--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-9-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6397462e4c2544451bdacfa2dbbac32f1f0f451..83e1bc858b9fb745348e39a369cf9bc169b32aa0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5332,6 +5332,37 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(master_transcoder);
        PIPE_CONF_CHECK_X(bigjoiner_pipes);
 
+       PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
+       PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
+       PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
+       PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
+       PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
+       PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
+       PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
+       PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
+       PIPE_CONF_CHECK_I(dsc.config.pic_width);
+       PIPE_CONF_CHECK_I(dsc.config.pic_height);
+       PIPE_CONF_CHECK_I(dsc.config.slice_width);
+       PIPE_CONF_CHECK_I(dsc.config.slice_height);
+       PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
+       PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
+       PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
+       PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
+       PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
+       PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
+       PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
+       PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
+       PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
+       PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
+       PIPE_CONF_CHECK_I(dsc.config.initial_offset);
+       PIPE_CONF_CHECK_I(dsc.config.final_offset);
+       PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
+       PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
+       PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
+       PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
+       PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
+       PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
+
        PIPE_CONF_CHECK_I(dsc.compression_enable);
        PIPE_CONF_CHECK_I(dsc.dsc_split);
        PIPE_CONF_CHECK_I(dsc.compressed_bpp);