ARM: dts: ux500: Adjust operating points to reality

The operating points should correspond to the actual frequencies
supported for the CPU. Other patches have fixed so these are
rounded and reported properly, this fixes the device trees to
match.

The Codina variant has a lower frequency than other devices so
indicate this in the device tree.

Cc: phone-devel@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/ste-db8500.dtsi
index 344d29853bf76f1300872822fd4ba6d0297f903d..b5b8ba9be55e9441f43266e0f05958836f191c09 100644 (file)
--- a/arch/arm/boot/dts/ste-db8500.dtsi
+++ b/arch/arm/boot/dts/ste-db8500.dtsi
@@ -5,11 +5,10 @@
 / {
        cpus {
                cpu@300 {
-                       /* cpufreq controls */
                        operating-points = <998400 0
-                                           800000 0
-                                           400000 0
-                                           200000 0>;
+                                           798720 0
+                                           399360 0
+                                           199680 0>;
                };
        };
 

diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/ste-db8520.dtsi
index 287804e9e1836775364650c402bf01fdf4fcf742..0c277a6d19140f4c2bc8f2c56385308010bb7284 100644 (file)
--- a/arch/arm/boot/dts/ste-db8520.dtsi
+++ b/arch/arm/boot/dts/ste-db8520.dtsi
@@ -5,11 +5,10 @@
 / {
        cpus {
                cpu@300 {
-                       /* cpufreq controls */
                        operating-points = <1152000 0
-                                           800000 0
-                                           400000 0
-                                           200000 0>;
+                                           798720 0
+                                           399360 0
+                                           199680 0>;
                };
        };
 

diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/ste-db9500.dtsi
index 0afff703191c67a4efac243914e60028e8867a46..4273d36e881de1ccfee53c6a67c210fc805b28df 100644 (file)
--- a/arch/arm/boot/dts/ste-db9500.dtsi
+++ b/arch/arm/boot/dts/ste-db9500.dtsi
@@ -5,11 +5,10 @@
 / {
        cpus {
                cpu@300 {
-                       /* cpufreq controls */
-                       operating-points = <1152000 0
-                                           800000 0
-                                           400000 0
-                                           200000 0>;
+                       operating-points = <998400 0
+                                           798720 0
+                                           399360 0
+                                           199680 0>;
                };
        };
 

diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
index ba7986988e87e2c2afc79bd5bee3f91b4db128fe..952606e607ed65052c7dcb7ad787475a06e4fdec 100644 (file)
--- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts
@@ -27,6 +27,18 @@
        model = "Samsung Galaxy Ace 2 (GT-I8160)";
        compatible = "samsung,codina", "st-ericsson,u8500";
 
+       cpus {
+               cpu@300 {
+                       /*
+                        * This has a frequency cap at ~800 MHz in the firmware.
+                        * (Changing this number here will not overclock it.)
+                        */
+                       operating-points = <798720 0
+                                           399360 0
+                                           199680 0>;
+               };
+       };
+
        chosen {
                stdout-path = &serial2;
        };