drm/amdgpu: add mc wptr addr support for mes

MES requires mc wptr address for usermode queues.
Export bo gart address for mc wptr address.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 521e35d93d677084f0046eb8e5cd582e29629d69..0c9cb493a85c3525be312a955b0f2c36e354b4f6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -675,6 +675,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
        queue_input.doorbell_offset = qprops->doorbell_off;
        queue_input.mqd_addr = queue->mqd_gpu_addr;
        queue_input.wptr_addr = qprops->wptr_gpu_addr;
+       queue_input.wptr_mc_addr = qprops->wptr_mc_addr;
        queue_input.queue_type = qprops->queue_type;
        queue_input.paging = qprops->paging;
        queue_input.is_kfd_process = 0;
@@ -802,6 +803,8 @@ amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
        props->hqd_base_gpu_addr = ring->gpu_addr;
        props->rptr_gpu_addr = ring->rptr_gpu_addr;
        props->wptr_gpu_addr = ring->wptr_gpu_addr;
+       props->wptr_mc_addr =
+               ring->mes_ctx->meta_data_mc_addr + ring->wptr_offs;
        props->queue_size = ring->ring_size;
        props->eop_gpu_addr = ring->eop_gpu_addr;
        props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL;
@@ -962,7 +965,8 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
        r = amdgpu_bo_create_kernel(adev,
                            sizeof(struct amdgpu_mes_ctx_meta_data),
                            PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
-                           &ctx_data->meta_data_obj, NULL,
+                           &ctx_data->meta_data_obj,
+                           &ctx_data->meta_data_mc_addr,
                            &ctx_data->meta_data_ptr);
        if (!ctx_data->meta_data_obj)
                return -ENOMEM;
@@ -976,7 +980,9 @@ int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data)
 {
        if (ctx_data->meta_data_obj)
-               amdgpu_bo_free_kernel(&ctx_data->meta_data_obj, NULL, NULL);
+               amdgpu_bo_free_kernel(&ctx_data->meta_data_obj,
+                                     &ctx_data->meta_data_mc_addr,
+                                     &ctx_data->meta_data_ptr);
 }
 
 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 85ebb5fdba0b51ecf7c08a8a40f4dd3bc1981554..074418c63e4b487bb4effcd31689569b1d69335c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -176,6 +176,7 @@ struct amdgpu_mes_queue_properties {
        uint64_t                hqd_base_gpu_addr;
        uint64_t                rptr_gpu_addr;
        uint64_t                wptr_gpu_addr;
+       uint64_t                wptr_mc_addr;
        uint32_t                queue_size;
        uint64_t                eop_gpu_addr;
        uint32_t                hqd_pipe_priority;
@@ -208,6 +209,7 @@ struct mes_add_queue_input {
        uint32_t        doorbell_offset;
        uint64_t        mqd_addr;
        uint64_t        wptr_addr;
+       uint64_t        wptr_mc_addr;
        uint32_t        queue_type;
        uint32_t        paging;
        uint32_t        gws_base;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
index c000f656aae5e4de5feafca3556ba253b9444bda..912a5be2ece6cd4058e1ac4cb5ca5a73f96dbd32 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
@@ -107,6 +107,7 @@ struct amdgpu_mes_ctx_meta_data {
 struct amdgpu_mes_ctx_data {
        struct amdgpu_bo        *meta_data_obj;
        uint64_t                meta_data_gpu_addr;
+       uint64_t                meta_data_mc_addr;
        struct amdgpu_bo_va     *meta_data_va;
        void                    *meta_data_ptr;
        uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 7dfc6ea21397bbaf97e76b470e1767f36f132270..89b99dc827a6a4e81eb6f3056d2e00cbf501dab1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -156,7 +156,13 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
                input->gang_global_priority_level;
        mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
        mes_add_queue_pkt.mqd_addr = input->mqd_addr;
-       mes_add_queue_pkt.wptr_addr = input->wptr_addr;
+
+       if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
+                       AMDGPU_MES_API_VERSION_SHIFT) >= 2)
+               mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
+       else
+               mes_add_queue_pkt.wptr_addr = input->wptr_addr;
+
        mes_add_queue_pkt.queue_type =
                convert_to_mes_queue_type(input->queue_type);
        mes_add_queue_pkt.paging = input->paging;

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 74a1f8a6f53f3fe574e7f5d18f695353aa6ab7d0..21e451acfa5989b1081634759a71b1c0632851c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -197,12 +197,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
                                        AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
        queue_input.doorbell_offset = q->properties.doorbell_off;
        queue_input.mqd_addr = q->gart_mqd_addr;
+       queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
 
        if (q->wptr_bo) {
                wptr_addr_off = (uint64_t)q->properties.write_ptr - (uint64_t)q->wptr_bo->kfd_bo->va;
-               queue_input.wptr_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
-       } else
-               queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
+               queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
+       }
 
        queue_input.is_kfd_process = 1;