media: ccs-pll: Fix condition for pre-PLL divider lower bound
authorSakari Ailus <sakari.ailus@linux.intel.com>
Tue, 7 Jul 2020 08:08:01 +0000 (10:08 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 7 Dec 2020 14:49:01 +0000 (15:49 +0100)
The lower bound of the pre-PLL divider was calculated based on OP SYS
clock frequency which is also affected by the OP SYS clock divider. This
is wrong. The right clock frequency is that of the PLL output clock.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/ccs-pll.c

index 584be36f8c66bb45ea74cd35f0bdf7ff28a69a44..b45e6b30c528c54401a1ce44b9f61d79ef45b004 100644 (file)
@@ -459,7 +459,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
                max_t(uint16_t, min_op_pre_pll_clk_div,
                      clk_div_even_up(
                              DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
-                                          op_lim_bk->max_sys_clk_freq_hz)));
+                                          op_lim_fr->max_pll_op_clk_freq_hz)));
        dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
                min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);