(0x001d43e0 + 0x00001800),
 };
 
-static const uint32_t ecc_umc_mcumc_status_addrs[] = {
-       (0x000143c2 + 0x00000000),
-       (0x000143c2 + 0x00000800),
-       (0x000143c2 + 0x00001000),
-       (0x000143c2 + 0x00001800),
-       (0x000543c2 + 0x00000000),
-       (0x000543c2 + 0x00000800),
-       (0x000543c2 + 0x00001000),
-       (0x000543c2 + 0x00001800),
-       (0x000943c2 + 0x00000000),
-       (0x000943c2 + 0x00000800),
-       (0x000943c2 + 0x00001000),
-       (0x000943c2 + 0x00001800),
-       (0x000d43c2 + 0x00000000),
-       (0x000d43c2 + 0x00000800),
-       (0x000d43c2 + 0x00001000),
-       (0x000d43c2 + 0x00001800),
-       (0x001143c2 + 0x00000000),
-       (0x001143c2 + 0x00000800),
-       (0x001143c2 + 0x00001000),
-       (0x001143c2 + 0x00001800),
-       (0x001543c2 + 0x00000000),
-       (0x001543c2 + 0x00000800),
-       (0x001543c2 + 0x00001000),
-       (0x001543c2 + 0x00001800),
-       (0x001943c2 + 0x00000000),
-       (0x001943c2 + 0x00000800),
-       (0x001943c2 + 0x00001000),
-       (0x001943c2 + 0x00001800),
-       (0x001d43c2 + 0x00000000),
-       (0x001d43c2 + 0x00000800),
-       (0x001d43c2 + 0x00001000),
-       (0x001d43c2 + 0x00001800),
-};
-
 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
                struct amdgpu_irq_src *src,
                unsigned type,