timeout-sec = <30>;
        };
 
+       v2m_clk24mhz: clk24mhz {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "v2m:clk24mhz";
+       };
+
+       v2m_refclk1mhz: refclk1mhz {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <1000000>;
+               clock-output-names = "v2m:refclk1mhz";
+       };
+
+       v2m_refclk32khz: refclk32khz {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <32768>;
+               clock-output-names = "v2m:refclk32khz";
+       };
+
        bus@8000000 {
                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                arm,v2m-memory-map = "rs1";
                        interrupts = <15>;
                };
 
-               v2m_clk24mhz: clk24mhz {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-                       clock-frequency = <24000000>;
-                       clock-output-names = "v2m:clk24mhz";
-               };
-
-               v2m_refclk1mhz: refclk1mhz {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-                       clock-frequency = <1000000>;
-                       clock-output-names = "v2m:refclk1mhz";
-               };
-
-               v2m_refclk32khz: refclk32khz {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-                       clock-frequency = <32768>;
-                       clock-output-names = "v2m:refclk32khz";
-               };
-
                iofpga@300000000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;