arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default
authorMichael Walle <mwalle@kernel.org>
Wed, 3 Apr 2024 10:15:45 +0000 (12:15 +0200)
committerNishanth Menon <nm@ti.com>
Wed, 10 Apr 2024 00:29:15 +0000 (19:29 -0500)
Device tree best practice is to disable any external interface in the
dtsi and just enable them if needed in the device tree. Thus, disable
the ethernet switch and its ports by default and just enable the ones
used by the EVMs in their device trees.

There is no functional change.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240403101545.3932437-1-mwalle@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
arch/arm64/boot/dts/ti/k3-j722s-evm.dts

index 7337a9e1353542bfcb8633ea1306defb54e4b476..88bc64111234b907ef2dd25fa661e1639aef0f23 100644 (file)
                assigned-clock-parents = <&k3_clks 13 11>;
                clock-names = "fck";
                power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
 
                dmas = <&main_pktdma 0xc600 15>,
                       <&main_pktdma 0xc601 15>,
                                label = "port1";
                                phys = <&phy_gmii_sel 1>;
                                mac-address = [00 00 00 00 00 00];
+                               status = "disabled";
                        };
 
                        cpsw_port2: port@2 {
                                label = "port2";
                                phys = <&phy_gmii_sel 2>;
                                mac-address = [00 00 00 00 00 00];
+                               status = "disabled";
                        };
                };
 
index 6694087b3665fd5cbd194df6ab87277e82bfeb14..6a9c99c5fb2a22d82d33d12639ca64fa03de78d0 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&main_rgmii1_pins_default>,
                    <&main_rgmii2_pins_default>;
+       status = "okay";
 };
 
 &cpsw_port1 {
        phy-mode = "rgmii-rxid";
        phy-handle = <&cpsw3g_phy0>;
+       status = "okay";
 };
 
 &cpsw_port2 {
        phy-mode = "rgmii-rxid";
        phy-handle = <&cpsw3g_phy1>;
+       status = "okay";
 };
 
 &cpsw3g_mdio {
index cee3a8661d5e3c82e932590f78546a10227c5603..4b36db949a520c15fb0d180cdf7c83c79e937480 100644 (file)
 &cpsw_port1 {
        phy-mode = "rgmii-rxid";
        phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
-       status = "disabled";
+       status = "okay";
 };
 
 &main_gpio1 {