drm/amdgpu: update HDP LS settings

Avoid unnecessary register programming on feature disablement.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
index 7a15e669b68db0517fc6f19c6aad62cbdb183457..5793977953cc41dc1016ab432ad50d145abc363b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c
@@ -90,45 +90,56 @@ static void hdp_v5_0_update_mem_power_gating(struct amdgpu_device *adev,
                                         RC_MEM_POWER_SD_EN, 0);
        WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 
-       /* only one clock gating mode (LS/DS/SD) can be enabled */
-       if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_LS_EN, enable);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_LS_EN, enable);
-       } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_DS_EN, enable);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_DS_EN, enable);
-       } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_SD_EN, enable);
-               /* RC should not use shut down mode, fallback to ds */
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
-                                                HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_DS_EN, enable);
-       }
-
-       /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
-        * be set for SRAM LS/DS/SD */
-       if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
-                             AMD_CG_SUPPORT_HDP_SD)) {
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                                IPH_MEM_POWER_CTRL_EN, 1);
-               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
-                                                RC_MEM_POWER_CTRL_EN, 1);
+       /* Already disabled above. The actions below are for "enabled" only */
+       if (enable) {
+               /* only one clock gating mode (LS/DS/SD) can be enabled */
+               if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                        HDP_MEM_POWER_CTRL,
+                                                        IPH_MEM_POWER_LS_EN, 1);
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                        HDP_MEM_POWER_CTRL,
+                                                        RC_MEM_POWER_LS_EN, 1);
+               } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                        HDP_MEM_POWER_CTRL,
+                                                        IPH_MEM_POWER_DS_EN, 1);
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                        HDP_MEM_POWER_CTRL,
+                                                        RC_MEM_POWER_DS_EN, 1);
+               } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                        HDP_MEM_POWER_CTRL,
+                                                        IPH_MEM_POWER_SD_EN, 1);
+                       /* RC should not use shut down mode, fallback to ds  or ls if allowed */
+                       if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS)
+                               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                                HDP_MEM_POWER_CTRL,
+                                                                RC_MEM_POWER_DS_EN, 1);
+                       else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)
+                               hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+                                                                HDP_MEM_POWER_CTRL,
+                                                                RC_MEM_POWER_LS_EN, 1);
+               }
+
+               /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
+                * be set for SRAM LS/DS/SD */
+               if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
+                                     AMD_CG_SUPPORT_HDP_SD)) {
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+                                                        IPH_MEM_POWER_CTRL_EN, 1);
+                       hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+                                                        RC_MEM_POWER_CTRL_EN, 1);
+                       WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
+               }
        }
 
-       WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
-
-       /* restore IPH & RC clock override after clock/power mode changing */
-       WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
+       /* disable IPH & RC clock override after clock/power mode changing */
+       hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
+                                    IPH_MEM_CLK_SOFT_OVERRIDE, 0);
+       hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
+                                    RC_MEM_CLK_SOFT_OVERRIDE, 0);
+       WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 }
 
 static void hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,