arm64: dts: qcom: msm8996-*: Clean up QUP and UART names

QUP and UART names start from 1. There are 6 QUPs and 2 UARTs
per BLSP. Let's not further confuse programmers by stating
otherwise.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 4212f5c6e8b6625f7a3bbc5c2863fc5ec0fe1833..6b3b6a4c061322597bdd6a105b7d568ae7344276 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -41,14 +41,14 @@
 
 / {
        aliases {
-               serial0 = &blsp2_uart1;
-               serial1 = &blsp2_uart2;
-               serial2 = &blsp1_uart1;
-               i2c0    = &blsp1_i2c2;
+               serial0 = &blsp2_uart2;
+               serial1 = &blsp2_uart3;
+               serial2 = &blsp1_uart2;
+               i2c0    = &blsp1_i2c3;
                i2c1    = &blsp2_i2c1;
-               i2c2    = &blsp2_i2c0;
-               spi0    = &blsp1_spi0;
-               spi1    = &blsp2_spi5;
+               i2c2    = &blsp2_i2c1;
+               spi0    = &blsp1_spi1;
+               spi1    = &blsp2_spi6;
        };
 
        chosen {
@@ -133,24 +133,24 @@
        };
 };
 
-&blsp1_i2c2 {
+&blsp1_i2c3 {
        /* On Low speed expansion */
        label = "LS-I2C0";
        status = "okay";
 };
 
-&blsp1_spi0 {
+&blsp1_spi1 {
        /* On Low speed expansion */
        label = "LS-SPI0";
        status = "okay";
 };
 
-&blsp1_uart1 {
+&blsp1_uart2 {
        label = "BT-UART";
        status = "okay";
        pinctrl-names = "default", "sleep";
-       pinctrl-0 = <&blsp1_uart1_default>;
-       pinctrl-1 = <&blsp1_uart1_sleep>;
+       pinctrl-0 = <&blsp1_uart2_default>;
+       pinctrl-1 = <&blsp1_uart2_sleep>;
 
        bluetooth {
                compatible = "qcom,qca6174-bt";
@@ -166,7 +166,7 @@
        status = "okay";
 };
 
-&blsp2_i2c0 {
+&blsp2_i2c1 {
        /* On High speed expansion */
        label = "HS-I2C2";
        status = "okay";
@@ -178,13 +178,13 @@
        status = "okay";
 };
 
-&blsp2_spi5 {
+&blsp2_spi6 {
        /* On High speed expansion */
        label = "HS-SPI1";
        status = "okay";
 };
 
-&blsp2_uart1 {
+&blsp2_uart2 {
        label = "LS-UART1";
        status = "okay";
        pinctrl-names = "default", "sleep";
@@ -192,7 +192,7 @@
        pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
 };
 
-&blsp2_uart2 {
+&blsp2_uart3 {
        label = "LS-UART0";
        status = "disabled";
        pinctrl-names = "default", "sleep";
@@ -428,7 +428,7 @@
                };
        };
 
-       blsp1_uart1_default: blsp1_uart1_default {
+       blsp1_uart2_default: blsp1_uart2_default {
                mux {
                        pins = "gpio41", "gpio42", "gpio43", "gpio44";
                        function = "blsp_uart2";
@@ -441,7 +441,7 @@
                };
        };
 
-       blsp1_uart1_sleep: blsp1_uart1_sleep {
+       blsp1_uart2_sleep: blsp1_uart2_sleep {
                mux {
                        pins = "gpio41", "gpio42", "gpio43", "gpio44";
                        function = "gpio";

diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
index 9b55eae39e3eb34776af5b73de3d98d4f07bc000..4f67aa48633ba4f27888d0f82ff3299937a657e1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts
@@ -17,7 +17,7 @@
        qcom,board-id = <0x00010018 0>;
 
        aliases {
-               serial0 = &blsp2_uart1;
+               serial0 = &blsp2_uart2;
        };
 
        chosen {
@@ -81,7 +81,7 @@
        };
 };
 
-&blsp2_uart1 {
+&blsp2_uart2 {
        status = "okay";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&blsp2_uart2_2pins_default>;

diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
index 5f46a1427f1f0ea596c20f5dc91156369fdeb162..1e1514e9158cca8ee12953a117d8cb81ee0cf69a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi
@@ -7,7 +7,7 @@
 
 / {
        aliases {
-               serial0 = &blsp2_uart1;
+               serial0 = &blsp2_uart2;
        };
 
        chosen {

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2f13d8e5d5212ed57a368f4e942ae67255991b29..0e564f88d1791507a0c4dce0285623504813bee0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2326,7 +2326,7 @@
                         bus-width = <4>;
                 };
 
-               blsp1_uart1: serial@7570000 {
+               blsp1_uart2: serial@7570000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0x07570000 0x1000>;
                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
@@ -2336,7 +2336,7 @@
                        status = "disabled";
                };
 
-               blsp1_spi0: spi@7575000 {
+               blsp1_spi1: spi@7575000 {
                        compatible = "qcom,spi-qup-v2.2.1";
                        reg = <0x07575000 0x600>;
                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -2351,7 +2351,7 @@
                        status = "disabled";
                };
 
-               blsp1_i2c2: i2c@7577000 {
+               blsp1_i2c3: i2c@7577000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x07577000 0x1000>;
                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -2366,7 +2366,7 @@
                        status = "disabled";
                };
 
-               blsp2_uart1: serial@75b0000 {
+               blsp2_uart2: serial@75b0000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0x075b0000 0x1000>;
                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -2376,7 +2376,7 @@
                        status = "disabled";
                };
 
-               blsp2_uart2: serial@75b1000 {
+               blsp2_uart3: serial@75b1000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0x075b1000 0x1000>;
                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
@@ -2386,7 +2386,7 @@
                        status = "disabled";
                };
 
-               blsp2_i2c0: i2c@75b5000 {
+               blsp2_i2c1: i2c@75b5000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x075b5000 0x1000>;
                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -2401,7 +2401,7 @@
                        status = "disabled";
                };
 
-               blsp2_i2c1: i2c@75b6000 {
+               blsp2_i2c2: i2c@75b6000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x075b6000 0x1000>;
                        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@@ -2416,7 +2416,7 @@
                        status = "disabled";
                };
 
-               blsp2_spi5: spi@75ba000{
+               blsp2_spi6: spi@75ba000{
                        compatible = "qcom,spi-qup-v2.2.1";
                        reg = <0x075ba000 0x600>;
                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;