drm/amdgpu/jpeg2.6: Add jpeg2.6 support

Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using
AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index c6724a0e0c436cf4870691122bcdab97f2f3f3e2..072774ae16bd48c4fe571b1dd3b6c42ea9016277 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -565,6 +565,26 @@ static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
        .set_powergating_state = jpeg_v2_5_set_powergating_state,
 };
 
+static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
+       .name = "jpeg_v2_6",
+       .early_init = jpeg_v2_5_early_init,
+       .late_init = NULL,
+       .sw_init = jpeg_v2_5_sw_init,
+       .sw_fini = jpeg_v2_5_sw_fini,
+       .hw_init = jpeg_v2_5_hw_init,
+       .hw_fini = jpeg_v2_5_hw_fini,
+       .suspend = jpeg_v2_5_suspend,
+       .resume = jpeg_v2_5_resume,
+       .is_idle = jpeg_v2_5_is_idle,
+       .wait_for_idle = jpeg_v2_5_wait_for_idle,
+       .check_soft_reset = NULL,
+       .pre_soft_reset = NULL,
+       .soft_reset = NULL,
+       .post_soft_reset = NULL,
+       .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
+       .set_powergating_state = jpeg_v2_5_set_powergating_state,
+};
+
 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_JPEG,
        .align_mask = 0xf,
@@ -595,6 +615,36 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 
+static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
+       .type = AMDGPU_RING_TYPE_VCN_JPEG,
+       .align_mask = 0xf,
+       .vmhub = AMDGPU_MMHUB_0,
+       .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
+       .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
+       .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
+       .emit_frame_size =
+               SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
+               SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
+               8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
+               18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
+               8 + 16,
+       .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
+       .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
+       .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
+       .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
+       .test_ring = amdgpu_jpeg_dec_ring_test_ring,
+       .test_ib = amdgpu_jpeg_dec_ring_test_ib,
+       .insert_nop = jpeg_v2_0_dec_ring_nop,
+       .insert_start = jpeg_v2_0_dec_ring_insert_start,
+       .insert_end = jpeg_v2_0_dec_ring_insert_end,
+       .pad_ib = amdgpu_ring_generic_pad_ib,
+       .begin_use = amdgpu_jpeg_ring_begin_use,
+       .end_use = amdgpu_jpeg_ring_end_use,
+       .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
+       .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
+       .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
 {
        int i;
@@ -602,8 +652,10 @@ static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
        for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
                if (adev->jpeg.harvest_config & (1 << i))
                        continue;
-
-               adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
+               if (adev->asic_type == CHIP_ARCTURUS)
+                       adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
+               else  /* CHIP_ALDEBARAN */
+                       adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs;
                adev->jpeg.inst[i].ring_dec.me = i;
                DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
        }
@@ -635,3 +687,12 @@ const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
                .rev = 0,
                .funcs = &jpeg_v2_5_ip_funcs,
 };
+
+const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
+{
+               .type = AMD_IP_BLOCK_TYPE_JPEG,
+               .major = 2,
+               .minor = 6,
+               .rev = 0,
+               .funcs = &jpeg_v2_6_ip_funcs,
+};

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
index 2b4087c026204a7e877ff61fb6c2ec6376143191..3b0aa29b98796f8320cbef7ce1b7e54a086611c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.h
@@ -25,5 +25,6 @@
 #define __JPEG_V2_5_H__
 
 extern const struct amdgpu_ip_block_version jpeg_v2_5_ip_block;
+extern const struct amdgpu_ip_block_version jpeg_v2_6_ip_block;
 
 #endif /* __JPEG_V2_5_H__ */