/* Offsets for the DesignWare specific registers */
 #define DW_UART_USR    0x1f /* UART Status Register */
 
+#define OCTEON_UART_USR        0x27 /* UART Status Register */
+
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE               BIT(6)
 
 
        if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
                /* Clear the USR */
-               (void)p->serial_in(p, d->usr_reg);
+               (void)p->serial_in(p, d->pdata->usr_reg);
 
                return 1;
        }
                        p->serial_out = dw8250_serial_outq;
                        p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
                        p->type = PORT_OCTEON;
-                       data->usr_reg = 0x27;
                        data->skip_autocfg = true;
                }
 #endif
                return -ENOMEM;
 
        data->data.dma.fn = dw8250_fallback_dma_filter;
-       data->usr_reg = DW_UART_USR;
        data->pdata = device_get_match_data(p->dev);
        p->private_data = &data->data;
 
 };
 
 static const struct dw8250_platform_data dw8250_dw_apb = {
+       .usr_reg = DW_UART_USR,
 };
 
 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
+       .usr_reg = OCTEON_UART_USR,
        .quirks = DW_UART_QUIRK_OCTEON,
 };
 
 static const struct dw8250_platform_data dw8250_armada_38x_data = {
+       .usr_reg = DW_UART_USR,
        .quirks = DW_UART_QUIRK_ARMADA_38X,
 };
 
 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
+       .usr_reg = DW_UART_USR,
 };
 
 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+       .usr_reg = DW_UART_USR,
        .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 };