arm64: dts: qcom: sm8250: add description of dcvsh interrupts

The change adds SM8250 cpufreq-epss controller interrupts for each
CPU core cluster.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211223075640.2924569-1-vladimir.zapolskiy@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index db57c115d262259989ad3bbbdfece395d2972816..88cd82ed75b7abf4ad519bed59a62ab8f55139d1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4571,7 +4571,10 @@
 
                        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
                        clock-names = "xo", "alternate";
-
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
                        #freq-domain-cells = <1>;
                };
        };