arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
and ETH1 respectively.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 9410796c8ad6b72de1d159bd2a48223399f3ab5f..c4faff0923800ab35ecb27371d61119ae8b4b529 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
@@ -94,6 +95,8 @@
                compatible = "ethernet-phy-id0022.1640",
                             "ethernet-phy-ieee802.3-c22";
                reg = <7>;
+               interrupt-parent = <&irqc>;
+               interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
                rxc-skew-psec = <2400>;
                txc-skew-psec = <2400>;
                rxdv-skew-psec = <0>;
@@ -120,6 +123,8 @@
                compatible = "ethernet-phy-id0022.1640",
                             "ethernet-phy-ieee802.3-c22";
                reg = <7>;
+               interrupt-parent = <&irqc>;
+               interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
                rxc-skew-psec = <2400>;
                txc-skew-psec = <2400>;
                rxdv-skew-psec = <0>;
@@ -171,7 +176,8 @@
                         <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
                         <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
                         <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
-                        <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+                        <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
+                        <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
        };
 
        eth1_pins: eth1 {
@@ -189,7 +195,8 @@
                         <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
                         <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
                         <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
-                        <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+                        <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
+                        <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
        };
 
        gpio-sd0-pwr-en-hog {