ep93xx: clock primitive print

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 2810eb5b2acaf0ad439498fad931d9914817ba9f..7de2a83c0e03cf4090b40758b0ba93a29bd2a021 100644 (file)
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -539,9 +539,102 @@ static void __init ep93xx_dma_clock_init(void)
        clk_m2m1.rate = clk_h.rate;
 }
 
+struct ep93xx_i2s_clk_reg {
+       union {
+               u32 __value;
+               struct {
+                       unsigned mdiv : 7;
+                       unsigned rsvd1 : 1;
+                       unsigned pdiv : 2;
+                       unsigned rsvd2 : 3;
+                       unsigned psel : 1;
+                       unsigned esel : 1;
+                       unsigned mena : 1;
+                       unsigned sdiv : 1;
+                       unsigned lrdiv : 2;
+                       unsigned spol : 1;
+                       unsigned drop : 1;
+                       unsigned rsvd3 : 8;
+                       unsigned oride : 1;
+                       unsigned slave : 1;
+                       unsigned sena : 1;
+               };
+       };
+};
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+static struct dentry *rootdir;
+static int inited = 0;
+static DEFINE_MUTEX(clk_debug_lock);
+static HLIST_HEAD(clk_debug_list);
+
+static void clk_summary_show_one(struct seq_file *s, struct clk_lookup *lookup,
+                                int level)
+{
+       int phase;
+       struct clk *c = lookup->clk;    
+
+       seq_printf(s, "%s - %s : %lu\n",
+                  lookup->dev_id ? lookup->dev_id : "",
+                  lookup->con_id ? lookup->con_id : "",
+                  clk_get_rate(c));
+}
+
+static int clk_summary_show(struct seq_file *s, void *data)
+{
+       int i;
+       u32 value;
+       struct ep93xx_i2s_clk_reg reg;
+
+       seq_puts(s, "                                 enable  prepare  protect                                duty  hardware\n");
+       seq_puts(s, "   clock                          count    count    count        rate   accuracy phase  cycle    enable\n");
+       seq_puts(s, "-------------------------------------------------------------------------------------------------------\n");
+
+       // clk_prepare_lock();
+
+       for (i = 0; i < ARRAY_SIZE(clocks); i++)
+                       clk_summary_show_one(s, &clocks[i], 0);
+
+       value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
+       reg.__value = value;
+       seq_printf(s, "I2S reg 0x%x, 0x%x\n", reg.__value, value);
+       seq_printf(s, "I2S reg mdiv=%u\n", reg.mdiv);
+       seq_printf(s, "I2S reg pdiv=%u\n", reg.pdiv);
+       seq_printf(s, "I2S reg psel=%u\n", reg.psel);
+       seq_printf(s, "I2S reg esel=%u\n", reg.esel);
+       seq_printf(s, "I2S reg mena=%u\n", reg.mena);
+       seq_printf(s, "I2S reg sdiv=%u\n", reg.sdiv);
+       seq_printf(s, "I2S reg lrdiv=%u\n", reg.lrdiv);
+       seq_printf(s, "I2S reg spol=%u\n", reg.spol);
+       seq_printf(s, "I2S reg drop=%u\n", reg.drop);
+       seq_printf(s, "I2S reg oride=%u\n", reg.oride);
+       seq_printf(s, "I2S reg slave=%u\n", reg.slave);
+       seq_printf(s, "I2S reg sena=%u\n", reg.sena);
+
+
+       // clk_prepare_unlock();
+
+       return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(clk_summary);
+
+static int __init clk_debug_init(void)
+{
+       rootdir = debugfs_create_dir("clk", NULL);
+
+       debugfs_create_file("clk_summary", 0444, rootdir, &clocks,
+                           &clk_summary_fops);
+
+       return 0;
+}
+late_initcall(clk_debug_init);
+#endif // CONFIG_DEBUG_FS
+
 static int __init ep93xx_clock_init(void)
 {
        u32 value;
+       struct ep93xx_i2s_clk_reg reg;
 
        /* Determine the bootloader configured pll1 rate */
        value = __raw_readl(EP93XX_SYSCON_CLKSET1);
@@ -582,6 +675,22 @@ static int __init ep93xx_clock_init(void)
                clk_f.rate / 1000000, clk_h.rate / 1000000,
                clk_p.rate / 1000000);
 
+       value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
+       reg.__value = value;
+       pr_info("I2S reg 0x%x, 0x%x\n", reg.__value, value);
+       pr_info("I2S reg mdiv=%u\n", reg.mdiv);
+       pr_info("I2S reg pdiv=%u\n", reg.pdiv);
+       pr_info("I2S reg psel=%u\n", reg.psel);
+       pr_info("I2S reg esel=%u\n", reg.esel);
+       pr_info("I2S reg mena=%u\n", reg.mena);
+       pr_info("I2S reg sdiv=%u\n", reg.sdiv);
+       pr_info("I2S reg lrdiv=%u\n", reg.lrdiv);
+       pr_info("I2S reg spol=%u\n", reg.spol);
+       pr_info("I2S reg drop=%u\n", reg.drop);
+       pr_info("I2S reg oride=%u\n", reg.oride);
+       pr_info("I2S reg slave=%u\n", reg.slave);
+       pr_info("I2S reg sena=%u\n", reg.sena);
+
        clkdev_add_table(clocks, ARRAY_SIZE(clocks));
        return 0;
 }