From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Mon, 14 Nov 2022 19:32:34 +0000 (-0500)
Subject: Merge drm/drm-next into drm-intel-next
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=002c6ca75289a4ac4f6738213dd2d258704886e4;p=linux.git

Merge drm/drm-next into drm-intel-next

Catch up on 6.1-rc cycle in order to solve the intel_backlight
conflict on linux-next.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---

002c6ca75289a4ac4f6738213dd2d258704886e4
diff --cc drivers/gpu/drm/i915/display/intel_backlight.c
index 0438071f58cf0,beba39a38c87c..71af88a70461c
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@@ -8,7 -8,8 +8,9 @@@
  #include <linux/pwm.h>
  #include <linux/string_helpers.h>
  
+ #include <acpi/video.h>
+ 
 +#include "i915_reg.h"
  #include "intel_backlight.h"
  #include "intel_backlight_regs.h"
  #include "intel_connector.h"
diff --cc drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fb0c61be350de,70177d3f2e945..5051d8ac7ae93
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@@ -7,8 -7,20 +7,21 @@@
  #define __INTEL_GT_REGS__
  
  #include "i915_reg_defs.h"
 +#include "display/intel_display_reg_defs.h"	/* VLV_DISPLAY_BASE */
  
+ #define MCR_REG(offset)	((const i915_mcr_reg_t){ .reg = (offset) })
+ 
+ /*
+  * The perf control registers are technically multicast registers, but the
+  * driver never needs to read/write them directly; we only use them to build
+  * lists of registers (where they're mixed in with other non-MCR registers)
+  * and then operate on the offset directly.  For now we'll just define them
+  * as non-multicast so we can place them on the same list, but we may want
+  * to try to come up with a better way to handle heterogeneous lists of
+  * registers in the future.
+  */
+ #define PERF_REG(offset)			_MMIO(offset)
+ 
  /* RPM unit config (Gen8+) */
  #define RPM_CONFIG0				_MMIO(0xd00)
  #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
diff --cc drivers/gpu/drm/i915/i915_reg_defs.h
index 1564f2c72c2a2,f1859046a9c48..be43580a69793
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@@ -132,21 -104,22 +132,20 @@@ typedef struct 
  
  #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
  
- #define INVALID_MMIO_REG _MMIO(0)
- 
- static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
- {
- 	return reg.reg;
- }
+ typedef struct {
+ 	u32 reg;
+ } i915_mcr_reg_t;
  
- static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
- {
- 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
- }
+ #define INVALID_MMIO_REG _MMIO(0)
  
- static inline bool i915_mmio_reg_valid(i915_reg_t reg)
- {
- 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
- }
+ /*
+  * These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're
+  * simply operations on the register's offset and don't care about the MCR vs
+  * non-MCR nature of the register.
+  */
+ #define i915_mmio_reg_offset(r) \
+ 	_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
+ #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
+ #define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
  
 -#define VLV_DISPLAY_BASE		0x180000
 -
  #endif /* __I915_REG_DEFS__ */