From: Arnd Bergmann Date: Thu, 6 Aug 2020 18:20:37 +0000 (+0200) Subject: ARM: s3c24xx: move regs-spi.h into spi driver X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0144e3fce3d601561fb51d0362316ca745c830df;p=linux.git ARM: s3c24xx: move regs-spi.h into spi driver The file is mostly specific to the driver, the few bits that are actually used by the platform code get moved to mach/map.h instead. Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Link: https://lore.kernel.org/r/20200806182059.2431-20-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski --- diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h index bca93112f57d6..a20c9fd0d855e 100644 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ b/arch/arm/mach-s3c24xx/include/mach/map.h @@ -86,6 +86,8 @@ #define S3C2410_PA_SPI (0x59000000) #define S3C2443_PA_SPI0 (0x52000000) #define S3C2443_PA_SPI1 S3C2410_PA_SPI +#define S3C2410_SPI1 (0x20) +#define S3C2412_SPI1 (0x100) /* SDI */ #define S3C2410_PA_SDI (0x5A000000) diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 8fe4d4670dcba..c3fb3e6c0dd86 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c @@ -37,7 +37,6 @@ #include #include #include -#include #include "common.h" #include "nand-core.h" diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 0607d29848414..0ed3a4b9fc12d 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -61,7 +61,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h deleted file mode 100644 index 6078443115660..0000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-spi.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Fetron GmbH - * - * S3C2410 SPI register definition - */ - -#ifndef __ASM_ARCH_REGS_SPI_H -#define __ASM_ARCH_REGS_SPI_H - -#define S3C2410_SPI1 (0x20) -#define S3C2412_SPI1 (0x100) - -#define S3C2410_SPCON (0x00) - -#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ -#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ -#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ -#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ -#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ -#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ -#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ - -#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ -#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ - -#define S3C2410_SPSTA (0x04) - -#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ -#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ -#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ -#define S3C2412_SPSTA_READY_ORG (1 << 3) - -#define S3C2410_SPPIN (0x08) - -#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ -#define S3C2410_SPPIN_RESERVED (1 << 1) -#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ - -#define S3C2410_SPPRE (0x0C) -#define S3C2410_SPTDAT (0x10) -#define S3C2410_SPRDAT (0x14) - -#endif /* __ASM_ARCH_REGS_SPI_H */ diff --git a/drivers/spi/spi-s3c24xx-fiq.S b/drivers/spi/spi-s3c24xx-fiq.S index e95d6282109e7..9d5f8f1e5e81f 100644 --- a/drivers/spi/spi-s3c24xx-fiq.S +++ b/drivers/spi/spi-s3c24xx-fiq.S @@ -12,10 +12,12 @@ #include #include -#include #include "spi-s3c24xx-fiq.h" +#define S3C2410_SPTDAT (0x10) +#define S3C2410_SPRDAT (0x14) + .text @ entry to these routines is as follows, with the register names diff --git a/drivers/spi/spi-s3c24xx-regs.h b/drivers/spi/spi-s3c24xx-regs.h new file mode 100644 index 0000000000000..f51464ab56778 --- /dev/null +++ b/drivers/spi/spi-s3c24xx-regs.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2004 Fetron GmbH + * + * S3C2410 SPI register definition + */ + +#ifndef __SPI_S3C2410_H +#define __SPI_S3C2410_H + +#define S3C2410_SPCON (0x00) + +#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ +#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ +#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ +#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ +#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ +#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ +#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ + +#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ +#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ + +#define S3C2410_SPSTA (0x04) + +#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ +#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ +#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ +#define S3C2412_SPSTA_READY_ORG (1 << 3) + +#define S3C2410_SPPIN (0x08) + +#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ +#define S3C2410_SPPIN_RESERVED (1 << 1) +#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ + +#define S3C2410_SPPRE (0x0C) +#define S3C2410_SPTDAT (0x10) +#define S3C2410_SPRDAT (0x14) + +#endif /* __SPI_S3C2410_H */ diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c index 2cb3b611c2949..0691248c7c0d9 100644 --- a/drivers/spi/spi-s3c24xx.c +++ b/drivers/spi/spi-s3c24xx.c @@ -21,10 +21,9 @@ #include #include -#include - #include +#include "spi-s3c24xx-regs.h" #include "spi-s3c24xx-fiq.h" /**