From: Christoph Müllner Date: Mon, 12 Jun 2023 11:10:30 +0000 (+0200) Subject: disas/riscv: Make rv_op_illegal a shared enum value X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=01b1361f84d55a86be486323836a29488b52e3a6;p=qemu.git disas/riscv: Make rv_op_illegal a shared enum value The enum value 'rv_op_illegal' does not represent an instruction, but is a catch-all value in case we have no match in the decoder. Let's make the value a shared one, so that other compile units can reuse it. Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Signed-off-by: Christoph Müllner Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis --- diff --git a/disas/riscv.c b/disas/riscv.c index 4a55348267..b6ced2a26a 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -23,7 +23,7 @@ #include "disas/riscv.h" typedef enum { - rv_op_illegal = 0, + /* 0 is reserved for rv_op_illegal. */ rv_op_lui = 1, rv_op_auipc = 2, rv_op_jal = 3, diff --git a/disas/riscv.h b/disas/riscv.h index 9288255915..debbe69239 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -191,6 +191,10 @@ typedef struct { const rvc_constraint *constraints; } rv_comp_data; +enum { + rv_op_illegal = 0 +}; + enum { rvcd_imm_nz = 0x1 };