From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Thu, 15 Feb 2024 16:04:23 +0000 (-0800)
Subject: Merge patch series "membarrier: riscv: Core serializing command"
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0420af54c2c2b7b3abbd986a41aded7cab0137ef;p=linux.git

Merge patch series "membarrier: riscv: Core serializing command"

RISC-V was lacking a membarrier implementation for the store/fetch
ordering, which is a bit tricky because of the deferred icache flushing
we use in RISC-V.

* b4-shazam-merge:
  membarrier: riscv: Provide core serializing command
  locking: Introduce prepare_sync_core_cmd()
  membarrier: Create Documentation/scheduler/membarrier.rst
  membarrier: riscv: Add full memory barrier in switch_mm()

Link: https://lore.kernel.org/r/20240131144936.29190-1-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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0420af54c2c2b7b3abbd986a41aded7cab0137ef