From: Kan Liang Date: Wed, 30 Jun 2021 21:08:30 +0000 (-0700) Subject: perf/x86/intel/uncore: Add Sapphire Rapids server PCU support X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0654dfdc7e1ca30d36810ab694712da3de18440c;p=linux.git perf/x86/intel/uncore: Add Sapphire Rapids server PCU support The PCU is the primary power controller for the Sapphire Rapids. Except the name, all the information can be retrieved from the discovery tables. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andi Kleen Link: https://lore.kernel.org/r/1625087320-194204-7-git-send-email-kan.liang@linux.intel.com --- diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 890a98279fca1..913cd7aca65de 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5633,6 +5633,10 @@ static struct intel_uncore_type spr_uncore_m2pcie = { .name = "m2pcie", }; +static struct intel_uncore_type spr_uncore_pcu = { + .name = "pcu", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { @@ -5640,7 +5644,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { &spr_uncore_iio, &spr_uncore_irp, &spr_uncore_m2pcie, - NULL, + &spr_uncore_pcu, NULL, NULL, NULL,