From: Li Zhijian Date: Mon, 3 Feb 2025 16:19:06 +0000 (+0000) Subject: hw/mem/cxl_type3: Fix special_ops memory leak on msix_init_exclusive_bar() failure X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=06953e7e5ea5e8fa0b7b704bdb66ab1e62f1f378;p=qemu.git hw/mem/cxl_type3: Fix special_ops memory leak on msix_init_exclusive_bar() failure Address a memory leak issue by ensuring `regs->special_ops` is freed when `msix_init_exclusive_bar()` encounters an error during CXL Type3 device initialization. Additionally, this patch renames err_address_space_free to err_msix_uninit for better clarity and logical flow Signed-off-by: Li Zhijian Signed-off-by: Jonathan Cameron Message-Id: <20250203161908.145406-4-Jonathan.Cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4775aab0d6..ff6861889b 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -893,7 +893,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) /* MSI(-X) Initialization */ rc = msix_init_exclusive_bar(pci_dev, CXL_T3_MSIX_VECTOR_NR, 4, NULL); if (rc) { - goto err_address_space_free; + goto err_free_special_ops; } for (i = 0; i < CXL_T3_MSIX_VECTOR_NR; i++) { msix_vector_use(pci_dev, i); @@ -907,7 +907,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) cxl_cstate->cdat.free_cdat_table = ct3_free_cdat_table; cxl_cstate->cdat.private = ct3d; if (!cxl_doe_cdat_init(cxl_cstate, errp)) { - goto err_free_special_ops; + goto err_msix_uninit; } pcie_cap_deverr_init(pci_dev); @@ -943,10 +943,10 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) err_release_cdat: cxl_doe_cdat_release(cxl_cstate); -err_free_special_ops: +err_msix_uninit: msix_uninit_exclusive_bar(pci_dev); +err_free_special_ops: g_free(regs->special_ops); -err_address_space_free: if (ct3d->dc.host_dc) { cxl_destroy_dc_regions(ct3d); address_space_destroy(&ct3d->dc.host_dc_as);