From: Johan Hovold Date: Fri, 15 Jul 2022 07:02:48 +0000 (+0200) Subject: ARM: dts: qcom: sdx65: reorder USB interrupts X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=079926b5a22ac92c4ac1e15e6cfb20a431802cb5;p=linux.git ARM: dts: qcom: sdx65: reorder USB interrupts Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold [bjorn: Split out from arm64 patch] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org --- diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7a193678b4f5b..8daefd50217a3 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -372,11 +372,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 19 IRQ_TYPE_EDGE_BOTH>, <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 18 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "ss_phy_irq", "dm_hs_phy_irq"; + <&pdc 18 IRQ_TYPE_EDGE_BOTH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; power-domains = <&gcc USB30_GDSC>;