From: Janakarajan Natarajan Date: Wed, 7 Nov 2018 20:59:07 +0000 (+0000) Subject: x86/cpufeatures: Add WBNOINVD feature definition X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=08e823c2c5899ef2de3aa1727233f1f19e8c1cc1;p=linux.git x86/cpufeatures: Add WBNOINVD feature definition Add a new cpufeature definition for the WBNOINVD instruction. The WBNOINVD instruction writes all modified cache lines in all levels of the cache associated with a processor to main memory while retaining the cached values. Both AMD and Intel support this instruction. Signed-off-by: Janakarajan Natarajan Signed-off-by: Borislav Petkov CC: David Woodhouse CC: Fenghua Yu CC: "H. Peter Anvin" CC: Ingo Molnar CC: Konrad Rzeszutek Wilk CC: Rudolf Marek CC: Thomas Gleixner CC: x86-ml Link: http://lkml.kernel.org/r/1541624211-32196-1-git-send-email-Janakarajan.Natarajan@amd.com --- diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 28c4a502b4197..39a48f06d39d0 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -281,6 +281,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */