From: Lad Prabhakar Date: Mon, 19 Jul 2021 14:38:09 +0000 (+0100) Subject: dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0b256c403d4082bafc681143913442288010277c;p=linux.git dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock Add P0_DIV2 core clock required for CANFD module. CANFD core clock is sourced from P0_DIV2 referenced from HW manual Rev.0.50. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index 0728ad07ff7a2..0bb17ff1a01a7 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -30,6 +30,7 @@ #define R9A07G044_CLK_P2 19 #define R9A07G044_CLK_AT 20 #define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 /* R9A07G044 Module Clocks */ #define R9A07G044_CA55_SCLK 0