From: George Shen Date: Thu, 9 Dec 2021 01:28:14 +0000 (-0500) Subject: drm/amd/display: Remove CR AUX RD Interval limit for LTTPR X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0d988e5de7aa5ee8865cbc664180ae67918a6b19;p=linux.git drm/amd/display: Remove CR AUX RD Interval limit for LTTPR [Why] DP spec specifies that DPRX shall use the read interval in the TRAINING_AUX_RD_INTERVAL_PHY_REPEATER LTTPR DPCD register. This register's bit definition is the same as the AUX read interval register for DPRX. [How} Remove logic which forces AUX read interval to 100us for repeaters when in LTTPR non-transparent mode. Tested-by: Daniel Wheeler Reviewed-by: Wesley Chalmers Acked-by: Rodrigo Siqueira Signed-off-by: George Shen Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 04878817e6225..9dc99929b0cdf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1544,9 +1544,6 @@ static enum link_training_result perform_clock_recovery_sequence( /* 3. wait receiver to lock-on*/ wait_time_microsec = lt_settings->cr_pattern_time; - if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) - wait_time_microsec = TRAINING_AUX_RD_INTERVAL; - if (link->dc->debug.apply_vendor_specific_lttpr_wa && (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)) { wait_time_microsec = 16000;