From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 30 Aug 2023 23:53:46 +0000 (-0700)
Subject: Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0e72db77672ff4758a31fb5259c754a7bb229751;p=linux.git

Merge tag 'soc-dt-6.6' of git://git./linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
 "These are the devicetree updates for Arm and RISC-V based SoCs, mainly
  from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
  Starfive.

  Only a few new SoC got added:

   - TI AM62P5, a variant of the existing Sitara AM62x family

   - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
     SoC.

   - Qualcomm ipq5018 is used in wireless access points

   - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
     platform.

  In total, 29 machines get added, which is low because of the summer
  break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
  Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
  these are development and reference boards.

  Despite not adding a lot of new machines, there are over 700 patches
  in total, most of which are cleanups and minor fixes"

* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
  arm64: dts: use capital "OR" for multiple licenses in SPDX
  ARM: dts: use capital "OR" for multiple licenses in SPDX
  arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
  ARM: dts: qcom: apq8064: add support to gsbi4 uart
  riscv: dts: change TH1520 files to dual license
  riscv: dts: thead: add BeagleV Ahead board device tree
  dt-bindings: riscv: Add BeagleV Ahead board compatibles
  ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
  ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
  dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
  ARM: dts: stm32: support display on stm32f746-disco board
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
  ARM: dts: stm32: add pin map for LTDC on stm32f7
  ARM: dts: stm32: add ltdc support on stm32f746 MCU
  arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Add PDC
  riscv: dts: starfive: fix jh7110 qspi sort order
  ...
---

0e72db77672ff4758a31fb5259c754a7bb229751
diff --cc arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 479948f8a4b75,7d28abb841ed6..92e62fe319290
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@@ -140,8 -140,28 +140,28 @@@
  	};
  };
  
+ /* TPM */
+ &ecspi2 {
+ 	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_ecspi2>;
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+ 	status = "okay";
+ 
+ 	tpm: tpm@0 {
+ 		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ 		interrupt-parent = <&gpio2>;
+ 		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&pinctrl_tpm>;
+ 		reg = <0>;
+ 		spi-max-frequency = <43000000>;
+ 	};
+ };
+ 
  &gpio1 {
 -	gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
 +	gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT",
  		"", "", "", "RESET_ETHPHY",
  		"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
  		"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
diff --cc arch/arm64/boot/dts/freescale/imx93.dtsi
index 1d8dd14b65cfa,4ec9df78f2050..6f85a05ee7e1a
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@@ -340,9 -379,29 +379,29 @@@
  
  			anatop: anatop@44480000 {
  				compatible = "fsl,imx93-anatop", "syscon";
 -				reg = <0x44480000 0x10000>;
 +				reg = <0x44480000 0x2000>;
  			};
  
+ 			tmu: tmu@44482000 {
+ 				compatible = "fsl,qoriq-tmu";
+ 				reg = <0x44482000 0x1000>;
+ 				clocks = <&clk IMX93_CLK_TMC_GATE>;
+ 				little-endian;
+ 				fsl,tmu-range = <0x800000da 0x800000e9
+ 						 0x80000102 0x8000012a
+ 						 0x80000166 0x800001a7
+ 						 0x800001b6>;
+ 				fsl,tmu-calibration = <0x00000000 0x0000000e
+ 						       0x00000001 0x00000029
+ 						       0x00000002 0x00000056
+ 						       0x00000003 0x000000a2
+ 						       0x00000004 0x00000116
+ 						       0x00000005 0x00000195
+ 						       0x00000006 0x000001b2>;
+ 				#thermal-sensor-cells = <1>;
+ 			};
+ 
+ 
  			adc1: adc@44530000 {
  				compatible = "nxp,imx93-adc";
  				reg = <0x44530000 0x10000>;