From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Fri, 17 May 2019 04:06:25 +0000 (+0530)
Subject: arm64: dts: rockchip: Enable SPI1 on Ficus
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0ee198ab08fe1b7cca93a81ad658954534963cb0;p=linux.git

arm64: dts: rockchip: Enable SPI1 on Ficus

Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:

CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 6b059bd7a04fe..ebe2ee77ba1f6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -146,6 +146,12 @@
 	};
 };
 
+&spi1 {
+	/* On both Low speed and High speed expansion */
+	cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
+	status = "okay";
+};
+
 &usbdrd_dwc3_0 {
 	dr_mode = "host";
 };