From: Claudiu Beznea Date: Mon, 11 Oct 2021 11:27:14 +0000 (+0300) Subject: clk: at91: clk-master: fix prescaler logic X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=0ef99f8202c5078a72c05af76bfaed2ea4daab19;p=linux.git clk: at91: clk-master: fix prescaler logic When prescaler value read from register is MASTER_PRES_MAX it means that the input clock will be divided by 3. Fix the code to reflect this. Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 6da9ae34313a1..e67bcd03a827e 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == 3 && characteristics->have_div3_pres) + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) pres = 3; else pres = (1 << pres);