From: Krzysztof Kozlowski Date: Wed, 9 Sep 2020 15:17:54 +0000 (+0200) Subject: arm64: dts: imx8mm-var-som-symphony: Adjust ethernet pin configuration X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=12cdf9d2c9f8b846ebca210c523fa6c3c5db0ac0;p=linux.git arm64: dts: imx8mm-var-som-symphony: Adjust ethernet pin configuration The Symphony board uses GPIO from expander as Ethernet PHY reset pin, not the GPIO1_IO9. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 4e811a7971fe1..daaed1a525a94 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -181,6 +181,26 @@ status = "disabled"; }; +&pinctrl_fec1 { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ + >; +}; + &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = <