From: Philippe Mathieu-Daudé Date: Sun, 1 Aug 2021 18:29:29 +0000 (+0200) Subject: target/mips: Merge 32-bit/64-bit Release6 decodetree definitions X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=12f79f11731194d7cb61c4a0d9b2de5416a773de;p=qemu.git target/mips: Merge 32-bit/64-bit Release6 decodetree definitions We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson --- diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index bf4001e574..70fa3dd57d 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,6 +1,5 @@ gen = [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), + decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), ] diff --git a/target/mips/tcg/mips32r6.decode b/target/mips/tcg/mips32r6.decode deleted file mode 100644 index 837c991edc..0000000000 --- a/target/mips/tcg/mips32r6.decode +++ /dev/null @@ -1,36 +0,0 @@ -# MIPS32 Release 6 instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daudé -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume II-A -# The MIPS32 Instruction Set Reference Manual, Revision 6.06 -# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) -# - -&rtype rs rt rd sa - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -LSA 000000 ..... ..... ..... 000 .. 000101 @lsa - -REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) - -REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 - -REMOVED 011111 ----- ----- ---------- 011001 # LWLE -REMOVED 011111 ----- ----- ---------- 011010 # LWRE -REMOVED 011111 ----- ----- ---------- 100001 # SWLE -REMOVED 011111 ----- ----- ---------- 100010 # SWRE - -REMOVED 100010 ----- ----- ---------------- # LWL -REMOVED 100110 ----- ----- ---------------- # LWR -REMOVED 101010 ----- ----- ---------------- # SWL -REMOVED 101110 ----- ----- ---------------- # SWR - -REMOVED 101111 ----- ----- ---------------- # CACHE -REMOVED 110000 ----- ----- ---------------- # LL -REMOVED 110011 ----- ----- ---------------- # PREF -REMOVED 111000 ----- ----- ---------------- # SC diff --git a/target/mips/tcg/mips64r6.decode b/target/mips/tcg/mips64r6.decode deleted file mode 100644 index b58d8009cc..0000000000 --- a/target/mips/tcg/mips64r6.decode +++ /dev/null @@ -1,27 +0,0 @@ -# MIPS64 Release 6 instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daudé -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume II-A -# The MIPS64 Instruction Set Reference Manual, Revision 6.06 -# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) -# - -&rtype rs rt rd sa !extern - -&REMOVED !extern - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa - -REMOVED 011010 ----- ----- ---------------- # LDL -REMOVED 011011 ----- ----- ---------------- # LDR -REMOVED 101100 ----- ----- ---------------- # SDL -REMOVED 101101 ----- ----- ---------------- # SDR - -REMOVED 110100 ----- ----- ---------------- # LLD -REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode new file mode 100644 index 0000000000..ed069c5166 --- /dev/null +++ b/target/mips/tcg/rel6.decode @@ -0,0 +1,49 @@ +# MIPS32 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# +# MIPS Architecture for Programmers Volume II-A +# The MIPS32 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) +# +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) + +&rtype rs rt rd sa + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa + +REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) + +REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 + +REMOVED 011010 ----- ----- ---------------- # LDL +REMOVED 011011 ----- ----- ---------------- # LDR + +REMOVED 011111 ----- ----- ---------- 011001 # LWLE +REMOVED 011111 ----- ----- ---------- 011010 # LWRE +REMOVED 011111 ----- ----- ---------- 100001 # SWLE +REMOVED 011111 ----- ----- ---------- 100010 # SWRE + +REMOVED 100010 ----- ----- ---------------- # LWL +REMOVED 100110 ----- ----- ---------------- # LWR +REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101100 ----- ----- ---------------- # SDL +REMOVED 101101 ----- ----- ---------------- # SDR +REMOVED 101110 ----- ----- ---------------- # SWR + +REMOVED 101111 ----- ----- ---------------- # CACHE + +REMOVED 110000 ----- ----- ---------------- # LL +REMOVED 110011 ----- ----- ---------------- # PREF +REMOVED 110100 ----- ----- ---------------- # LLD +REMOVED 111000 ----- ----- ---------------- # SC +REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 0354370927..ae2e023a81 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -13,9 +13,8 @@ #include "exec/helper-gen.h" #include "translate.h" -/* Include the auto-generated decoder. */ -#include "decode-mips32r6.c.inc" -#include "decode-mips64r6.c.inc" +/* Include the auto-generated decoders. */ +#include "decode-rel6.c.inc" bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) { @@ -31,13 +30,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a) static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) { - return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); -} - -bool decode_isa_rel6(DisasContext *ctx, uint32_t insn) -{ - if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) { - return true; + if (TARGET_LONG_BITS != 64) { + return false; } - return decode_mips32r6(ctx, insn); + return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); }