From: Ian Rogers Date: Thu, 13 Apr 2023 13:29:33 +0000 (-0700) Subject: perf vendor events intel: Fix uncore topics for broadwell X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=141825578a2467294752d2952c166116e32af2ca;p=linux.git perf vendor events intel: Fix uncore topics for broadwell Reduce the number of 'uncore-other' topic classifications, move to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json index fcb15b880bad2..c5cc43825cb9f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json @@ -6,7 +6,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", @@ -15,7 +15,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", @@ -24,7 +24,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", @@ -33,7 +33,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", @@ -42,7 +42,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", @@ -51,7 +51,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in M-state", @@ -60,7 +60,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state", @@ -69,7 +69,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state", @@ -78,7 +78,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", @@ -87,7 +87,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state", @@ -96,7 +96,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -104,7 +104,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -112,7 +112,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -120,7 +120,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -128,6 +128,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json new file mode 100644 index 0000000000000..64af685274a2a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json @@ -0,0 +1,61 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json index 368a958a18a0f..58be90d7cc932 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -1,63 +1,4 @@ [ - { - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", - "PerPkg": "1", - "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", - "PerPkg": "1", - "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", "EventCode": "0xff",