From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 29 Feb 2024 15:10:36 +0000 (+0100)
Subject: Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk... 
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=1422eb8585c1bc1dfbab29e82fda5840cd0e2567;p=linux.git

Merge tag 'samsung-dt64-6.9' of https://git./linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.9

Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:

1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
   several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.

Exynos850:
1. SPI and DMA controllers (PL330).

* tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: fsd: Add fifosize for UART in Device Tree
  arm64: dts: exynos: gs101: minor whitespace cleanup
  arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
  arm64: dts: exynos: gs101: define USI12 with I2C configuration
  arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
  dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
  arm64: dts: exynos: Add SPI nodes for Exynos850
  arm64: dts: exynos: Add PDMA node for Exynos850
  arm64: dts: exynos: gs101: use correct clocks for usi_uart
  arm64: dts: exynos: gs101: use correct clocks for usi8
  arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
  arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
  arm64: dts: exynos: gs101: define USI8 with I2C configuration
  arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
  arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
  arm64: dts: exynos: gs101: remove reg-io-width from serial
  arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
  dt-bindings: clock: exynos850: Add PDMA clocks
  dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit

Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---

1422eb8585c1bc1dfbab29e82fda5840cd0e2567
diff --cc Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index ca7fdada3ff24,4a74d19cf4889..1d2bcea41c858
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@@ -85,9 -87,31 +87,31 @@@ allOf
  
          clock-names:
            items:
 -            - const: dout_cmu_misc_bus
 -            - const: dout_cmu_misc_sss
 +            - const: bus
 +            - const: sss
  
+   - if:
+       properties:
+         compatible:
+           contains:
+             enum:
+               - google,gs101-cmu-peric0
+               - google,gs101-cmu-peric1
+ 
+     then:
+       properties:
+         clocks:
+           items:
+             - description: External reference clock (24.576 MHz)
+             - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
+             - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
+ 
+         clock-names:
+           items:
+             - const: oscclk
+             - const: bus
+             - const: ip
+ 
  additionalProperties: false
  
  examples:
diff --cc arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d838e3a7af6e5,7bca92bc1f8d1..55e6bcb3689e9
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@@ -289,9 -281,29 +281,29 @@@
  			#clock-cells = <1>;
  			clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
  				 <&cmu_top CLK_DOUT_CMU_MISC_SSS>;
 -			clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
 +			clock-names = "bus", "sss";
  		};
  
+ 		timer@10050000 {
+ 			compatible = "google,gs101-mct",
+ 				     "samsung,exynos4210-mct";
+ 			reg = <0x10050000 0x800>;
+ 			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
+ 				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
+ 			clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
+ 			clock-names = "fin_pll", "mct";
+ 		};
+ 
  		watchdog_cl0: watchdog@10060000 {
  			compatible = "google,gs101-wdt";
  			reg = <0x10060000 0x100>;