From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Date: Wed, 20 Nov 2019 00:22:54 +0000 (-0800)
Subject: tools/power/x86/intel-speed-select: Display TRL buckets for just base config level
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=1434a3d357d656d4b11fcbdc9b6c35dc673292a0;p=linux.git

tools/power/x86/intel-speed-select: Display TRL buckets for just base config level

When only base config level is present, this tool is displaying TRL
(Turbo-ratio-limits) by reading legacy MSR. In this case, also present
core count for TRL by reading MSR 0x1AE.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---

diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c
index aa19c9998e6cd..d14c7bcd327af 100644
--- a/tools/power/x86/intel-speed-select/isst-core.c
+++ b/tools/power/x86/intel-speed-select/isst-core.c
@@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev)
 			}
 
 			isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores);
+			isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info);
 			continue;
 		}