From: Peter Maydell Date: Mon, 17 Jun 2019 14:35:21 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190617' into... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=144ecc7f1a12504e8a134d1cb6d88764f75ae36c;p=qemu.git Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190617' into staging target-arm queue: * support large kernel images in bootloader (by avoiding putting the initrd over the top of them) * correctly disable FPU/DSP in the CPU for the mps2-an521, musca-a boards * arm_gicv3: Fix decoding of ID register range * arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 * some code cleanups following on from the VFP decodetree conversion * Only implement doubles if the FPU supports them (so we now correctly model Cortex-M4, -M33 as single precision only) # gpg: Signature made Mon 17 Jun 2019 15:33:01 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell " [ultimate] # gpg: aka "Peter Maydell " [ultimate] # gpg: aka "Peter Maydell " [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190617: (24 commits) target/arm: Only implement doubles if the FPU supports them target/arm: Fix typos in trans function prototypes target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm target/arm: Move vfp_expand_imm() to translate.[ch] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 hw/intc/arm_gicv3: Fix decoding of ID register range hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property target/arm: Allow VFP and Neon to be disabled via a CPU property ... Signed-off-by: Peter Maydell --- 144ecc7f1a12504e8a134d1cb6d88764f75ae36c