From: Dragan Mladjenovic Date: Wed, 4 May 2022 11:04:00 +0000 (+0200) Subject: target/mips: Fix emulation of nanoMIPS BNEC[32] instruction X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=14668cfaaf4d6f818d9e6b58dd44b75842654e2a;p=qemu.git target/mips: Fix emulation of nanoMIPS BNEC[32] instruction If both rs and rt are the same register, the nanoMIPS instruction BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and there is no delay slot). This commit provides such behavior. Without this commit, this scenario results in an incorrect behavior. Signed-off-by: Dragan Mladjenovic Signed-off-by: Stefan Pejic Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220504110403.613168-5-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé --- diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 941cfaa6bb..1ee5c8c8d4 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4528,7 +4528,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) switch (extract32(ctx->opcode, 14, 2)) { case NM_BNEC: check_nms(ctx); - gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s); + if (rs == rt) { + /* NOP */ + ctx->hflags |= MIPS_HFLAG_FBNSLOT; + } else { + gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s); + } break; case NM_BLTC: if (rs != 0 && rt != 0 && rs == rt) {