From: Andrew Jones Date: Thu, 15 Feb 2024 22:39:53 +0000 (-0300) Subject: target/riscv: Reset henvcfg to zero X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=148189ff1313e995a0a84957c496ff92965151a2;p=qemu.git target/riscv: Reset henvcfg to zero The hypervisor should decide what it wants to enable. Zero all configuration enable bits on reset. Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension") missed one reference to 'hade'. Change it now. Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address translation") Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension") Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4c4fa79145..5507c11161 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + env->henvcfg = 0; /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4e8ac13b9..cc9cef3d85 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2133,7 +2133,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, /* * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 - * henvcfg.hade is read_only 0 when menvcfg.hade = 0 + * henvcfg.adue is read_only 0 when menvcfg.adue = 0 */ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | env->menvcfg);