From: Tom Musta <tommusta@gmail.com>
Date: Wed, 12 Nov 2014 21:46:01 +0000 (-0600)
Subject: target-ppc: mffs. Should Set CR1 from FPSCR Bits
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=14ba79c73a1c2db78becef171ec2f73606c1d7e1;p=qemu.git

target-ppc: mffs. Should Set CR1 from FPSCR Bits

Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 35c3a16091..32c9f49fe0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2504,7 +2504,9 @@ static void gen_mffs(DisasContext *ctx)
     }
     gen_reset_fpstatus();
     tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
-    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+    if (unlikely(Rc(ctx->opcode))) {
+        gen_set_cr1_from_fpscr(ctx);
+    }
 }
 
 /* mtfsb0 */