From: Chris Park Date: Thu, 26 May 2022 03:22:11 +0000 (-0400) Subject: drm/amd/display: Switch to correct DTO on HDMI X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=15360d7fc35b6b0f46240659a129c9255345a41d;p=linux.git drm/amd/display: Switch to correct DTO on HDMI [Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Pass HDMI parameter for HDMI stream, and select correct DTO. Signed-off-by: Chris Park Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index c0989a04d025d..5b87f937554d3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -323,6 +323,8 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, if (pipe_ctx->stream_res.audio != NULL) dto_params.req_audio_dtbclk_khz = 24000; } + if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) + dto_params.is_hdmi = true; dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 152a76ad7957b..12fc3afd9acd4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -171,6 +171,9 @@ void dccg32_set_dtbclk_dto( REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], DTBCLK_DTO_ENABLE[params->otg_inst], 0, PIPE_DTO_SRC_SEL[params->otg_inst], 1); + if (params->is_hdmi) + REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], + PIPE_DTO_SRC_SEL[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); @@ -188,6 +191,7 @@ static void dccg32_set_valid_pixel_rate( dto_params.ref_dtbclk_khz = ref_dtbclk_khz; dto_params.otg_inst = otg_inst; dto_params.pixclk_khz = pixclk_khz; + dto_params.is_hdmi = true; dccg32_set_dtbclk_dto(dccg, &dto_params); }