From: Palmer Dabbelt <palmer@sifive.com>
Date: Wed, 25 Jul 2018 00:17:14 +0000 (-0700)
Subject: RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=1760debb51f73ed3e089c8d4e847554901dee4bb;p=linux.git

RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}

These are just hard coded in the RISC-V port, which doesn't make any
sense.  We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.

Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 0bc86e5f8f3fb..cb35ffd8ec6be 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 {
 	this_leaf->level = level;
 	this_leaf->type = type;
-	/* not a sector cache */
-	this_leaf->physical_line_partition = 1;
-	/* TODO: Add to DTS */
-	this_leaf->attributes =
-		CACHE_WRITE_BACK
-		| CACHE_READ_ALLOCATE
-		| CACHE_WRITE_ALLOCATE;
 }
 
 static int __init_cache_level(unsigned int cpu)