From: AngeloGioacchino Del Regno Date: Wed, 14 Dec 2022 13:11:16 +0000 (+0100) Subject: arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1 controller X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=1bd1d10d1c0cbb82ae42c5255821202e045e4c2b;p=linux.git arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1 controller Despite there being some flexibility regarding the P0/P1 connections, especially for TL and PERI, we must use P1 clocks on pcie1 otherwise we'll be dealing with unclocked access. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221214131117.108008-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c486..e61944510b8e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1258,9 +1258,9 @@ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, <&clk26m>, - <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, /* Designer has connect pcie1 with peri_mem_p0 clock */ <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; clock-names = "pl_250m", "tl_26m", "tl_96m",